FPGA Design Automation: A Survey
By Deming Chen, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, dchen@uiuc.edu | Jason Cong, Department of Computer Science, University of California at Los Angeles, cong@cs.ucla.edu | Peichen Pan, Magma Design Automation, Inc., peichen@magma-da.com
Abstract
Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology over the past two decades. The purpose of this paper is to meet the demand for an up-to-date comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5–10 years. The paper focuses on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow which includes: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. We hope that this paper can be used both as a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.
FPGA Design Automation
FPGA Design Automation: A Survey is an up-to-date comprehensive survey/tutorial of FPGA design automation, with an emphasis on the recent developments within the past 5 to 10 years. The focus is on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. FPGA Design Automation: A Survey can be used as both a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.