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"Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic."

Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang (2012)

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DOI: 10.1145/2159542.2159548

access: closed

type: Journal Article

metadata version: 2018-11-06

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  - https://dblp.org/rec/journals/todaes/WengKC12
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang:
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ACM Trans. Design Autom. Electr. Syst. 17(2): 16:1-16:15 (2012)

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