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"Generating reduced order models using subspace iteration for linear RLC ..."

J. V. R. Ravindra, M. B. Srinivas (2007)

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DOI: 10.4108/ICST.NANONET2007.2084

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - https://dblp.org/rec/conf/nanonet/RavindraS07
J. V. R. Ravindra, M. B. Srinivas:
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net 2007: 25

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