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"A VLSI Design Environment in PROLOG."

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Peter B. Reintjes (1988)

Trier

Dagstuhl

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DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2013-11-29

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  dblp key:
  - conf/iclp/Reintjes88
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  persistent URL:
  - https://dblp.org/rec/conf/iclp/Reintjes88
Peter B. Reintjes:
A VLSI Design Environment in PROLOG. ICLP/SLP 1988: 70-81

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last updated on 2013-11-29 14:57 CET by the dblp team

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