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"A Parallelized Iterative Improvement Approach to Area Optimization for ..."

Gai Liu, Zhiru Zhang (2017)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2017-02-03

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  dblp key:
  - conf/fpga/LiuZ17
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  - https://dblp.org/rec/conf/fpga/LiuZ17
Gai Liu, Zhiru Zhang:
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. FPGA 2017: 147-156

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