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"Architecture-aware Memory Access Scheduling for High-throughput Cascaded ..."

Hsiang-Chih Hsiao et al. (2019)

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DOI: 10.1109/DDECS.2019.8724671

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-03

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  dblp key:
  - conf/ddecs/HsiaoCWSC19
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  - https://dblp.org/rec/conf/ddecs/HsiaoCWSC19
Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen:
Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. DDECS 2019: 1-4

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