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"Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in ..."

M. Rullán et al. (1996)

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DOI: 10.1109/EDTC.1996.494360

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-11

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  dblp key:
  - conf/date/RullanFOMR96
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  persistent URL:
  - https://dblp.org/rec/conf/date/RullanFOMR96
M. Rullán, Carles Ferrer, Joan Oliver, Diego Mateo, Antonio Rubio:
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design. ED&TC 1996: 584-588

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