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"A 10-Gb/s CMOS clock and data recovery circuit with an analog phase ..."

Rainer Kreienkamp et al. (2003)

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DOI: 10.1109/CICC.2003.1249362

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-15

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  - https://dblp.org/rec/conf/cicc/KreienkampLZA03
Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama:
A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. CICC 2003: 73-76

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