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"Modified standard cell methodology for VLSI layout compaction."

Ehecatl Joel Chavez-Martinez, Moises Chavez-Martinez, Marco Antonio Gurrola-Navarro (2012)

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DOI: 10.1109/ICEEE.2012.6421201

access: closed

type: Conference or Workshop Paper

metadata version: 2017-09-16

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  - conf/cce/Chavez-MartinezCG12
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  - https://dblp.org/rec/conf/cce/Chavez-MartinezCG12
Ehecatl Joel Chavez-Martinez, Moises Chavez-Martinez, Marco Antonio Gurrola-Navarro:
Modified standard cell methodology for VLSI layout compaction. CCE 2012: 1-6

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