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"A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using ..."

Kai Zhang et al. (1999)

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DOI: 10.1109/ASPDAC.1999.760016

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/aspdac/ZhangSTH99
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  - https://dblp.org/rec/conf/aspdac/ZhangSTH99
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi:
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. ASP-DAC 1999: 291-294

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