default search action

combined dblp search
author search
venue search
publication search

ask others

"SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems."

Weixun Wang, Prabhat Mishra, Ann Gordon-Ross (2009)

> Home

Details and statistics

DOI: 10.1109/VLSI.DESIGN.2009.66

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/WangMG09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/WangMG09
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross:
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. VLSI Design 2009: 547-552

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.