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"TileNET: Scalable Architecture for High-Throughput Ternary Convolution ..."

Sahu Sai Vikram et al. (2018)

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DOI: 10.1109/VLSID.2018.113

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/VikramPMP18
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/VikramPMP18
Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna:
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. VLSID 2018: 461-462

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