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"Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs."

Jatan C. Shah, Sachin S. Sapatnekar (1996)

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DOI: 10.1109/ICVD.1996.489633

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/ShahS96
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ShahS96
Jatan C. Shah, Sachin S. Sapatnekar:
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. VLSI Design 1996: 346-351

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