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"New design on 2×VDD-tolerant power-rail ESD clamp circuit with low ..."

Chih-Ting Yeh, Ming-Dou Ker (2012)

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DOI: 10.1109/VLSI-DAT.2012.6212606

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Chih-Ting Yeh, Ming-Dou Ker:
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT 2012: 1-4

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