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"High speed DDR2/3 PHY and dual CPU core design for 28nm SoC."

Kevin Ho et al. (2012)

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DOI: 10.1109/VLSI-DAT.2012.6212637

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/vlsi-dat/HoCCL12
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  - https://dblp.org/rec/conf/vlsi-dat/HoCCL12
Kevin Ho, Tsung-Yi Chou, Po-Kai Chen, David J. Liou:
High speed DDR2/3 PHY and dual CPU core design for 28nm SoC. VLSI-DAT 2012: 1-5

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