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Dmitry V. Ponomarev
Dmitry Ponomarev 0001
Person information
- affiliation: Binghamton University, Vestal, NY, USA
Other persons with the same name
- Dmitry Ponomarev 0002
— Vienna University of Technology, Austria (and 1 more)
- Dmitry Ponomarev 0003 — unknown
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2020 – today
- 2024
- [c83]Kerem Arikan, Abraham Farrell, Williams Zhang Cen, Jack McMahon, Barry Williams, Yu David Liu, Nael B. Abu-Ghazaleh, Dmitry Ponomarev:
TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs. NDSS 2024 - 2022
- [j24]Md. Shohidul Islam
Efficient Hardware Malware Detectors That are Resilient to Adversarial Evasion. IEEE Trans. Computers 71(11): 2872-2887 (2022) - [c82]Daniel Townley, Kerem Arikan, Yu David Liu, Dmitry Ponomarev, Oguz Ergin:
Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks. USENIX Security Symposium 2022: 2839-2856 - 2021
- [c81]Ali Eker, David Timmerman, Barry Williams, Kenneth Chiu, Dmitry Ponomarev:
GVT-Guided Demand-Driven Scheduling in Parallel Discrete Event Simulation. ICPP 2021: 22:1-22:10 - [c80]Ali Eker, Yehia Arafa, Abdel-Hameed A. Badawy, Nandakishore Santhi
Load-Aware Dynamic Time Synchronization in Parallel Discrete Event Simulation. SIGSIM-PADS 2021: 95-105 - [c79]Barry Williams, Ali Eker, Kenneth Chiu, Dmitry Ponomarev:
High-Performance PDES on Manycore Clusters. SIGSIM-PADS 2021: 153-164 - [c78]Sarp Özdemir
Track Conventions, Not Attack Signatures: Fortifying X86 ABI and System Call Interfaces to Mitigate Code Reuse Attacks. SEED 2021: 176-188 - 2020
- [j23]Khaled N. Khasawneh
EnsembleHMD: Accurate Hardware Malware Detectors with Specialized Ensemble Classifiers. IEEE Trans. Dependable Secur. Comput. 17(3): 620-633 (2020) - [c77]Aisha Hasan, Ryan Riley, Dmitry Ponomarev:
Port or Shim? Stress Testing Application Performance on Intel SGX. IISWC 2020: 123-133 - [c76]Ali Eker, Barry Williams, Kenneth Chiu, Dmitry Ponomarev:
Demand-Driven PDES: Exploiting Locality in Simulation Models. SIGSIM-PADS 2020: 39-48
2010 – 2019
- 2019
- [c75]Daniel Townley, Dmitry Ponomarev:
SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors. PACT 2019: 43-54 - [c74]Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song
SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation. DAC 2019: 60 - [c73]Ali Eker, Barry Williams, Kenneth Chiu, Dmitry Ponomarev:
Controlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Many-Core Clusters. ICPP 2019: 64:1-64:10 - [c72]Atsuko Shimizu, Daniel Townley, Mohit Joshi, Dmitry Ponomarev:
EA-PLRU: Enclave-Aware Cache Replacement. HASP@ISCA 2019: 5:1-5:8 - [c71]Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
LATCH: A Locality-Aware Taint CHecker. MICRO 2019: 969-982 - 2018
- [j22]Dmitry Evtyushkin
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications. IEEE Trans. Dependable Secur. Comput. 15(3): 437-451 (2018) - [c70]Dmitry Evtyushkin, Ryan Riley, Nael B. Abu-Ghazaleh
BranchScope: A New Side-Channel Attack on Directional Branch Predictor. ASPLOS 2018: 693-707 - [c69]Ali Eker, Barry Williams, Nitesh Mishra, Dushyant Thakur, Kenneth Chiu, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
Performance Implications of Global Virtual Time Algorithms on a Knights Landing Processor. DS-RT 2018: 87-96 - [i1]Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh:
SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation. CoRR abs/1806.05179 (2018) - 2017
- [c68]Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. DAC 2017: 7:1-7:6 - [c67]Jesse Elwell, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
Hardening extended memory access control schemes with self-verified address spaces. ICCAD 2017: 392-399 - [c66]Khaled N. Khasawneh, Nael B. Abu-Ghazaleh
RHMD: evasion-resilient hardware malware detectors. MICRO 2017: 315-327 - [c65]Barry Williams, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
Performance Characterization of Parallel Discrete Event Simulation on Knights Landing Processor. SIGSIM-PADS 2017: 121-132 - 2016
- [j21]Jesse Elwell
Rethinking Memory Permissions for Protection Against Cross-Layer Attacks. ACM Trans. Archit. Code Optim. 12(4): 56:1-56:27 (2016) - [j20]Dmitry Evtyushkin
Understanding and Mitigating Covert Channels Through Branch Predictors. ACM Trans. Archit. Code Optim. 13(1): 10:1-10:23 (2016) - [j19]Meltem Ozsoy, Khaled N. Khasawneh, Caleb Donovick
Hardware-Based Malware Detection Using Low-Level Architectural Features. IEEE Trans. Computers 65(11): 3332-3344 (2016) - [c64]Dmitry Evtyushkin, Dmitry V. Ponomarev:
Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations. CCS 2016: 843-857 - [c63]Mehmet Kayaalp, Nael B. Abu-Ghazaleh
A high-resolution side-channel attack on last-level cache. DAC 2016: 72:1-72:6 - [c62]Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh
Jump over ASLR: Attacking branch predictors to bypass ASLR. MICRO 2016: 40:1-40:13 - 2015
- [j18]Mehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh
Signature-Based Protection from Code Reuse Attacks. IEEE Trans. Computers 64(2): 533-546 (2015) - [j17]Jingjing Wang, Nael B. Abu-Ghazaleh
AIR: Application-Level Interference Resilience for PDES on Multicore Systems. ACM Trans. Model. Comput. Simul. 25(3): 19:1-19:25 (2015) - [c61]Meltem Ozsoy, Caleb Donovick
Malware-aware processors: A framework for efficient online malware detection. HPCA 2015: 651-661 - [c60]Jingjing Wang, Nael B. Abu-Ghazaleh
Controlled Contention: Balancing Contention and Reservation in Multicore Application Scheduling. IPDPS 2015: 946-955 - [c59]Dmitry Evtyushkin
Covert channels through branch predictors: a feasibility study. HASP@ISCA 2015: 5:1-5:8 - [c58]Khaled N. Khasawneh, Meltem Ozsoy, Caleb Donovick
Ensemble Learning for Low-Level Hardware-Supported Malware Detection. RAID 2015: 3-25 - 2014
- [j16]Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors. IEEE Trans. Computers 63(2): 484-496 (2014) - [j15]Mehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh
Efficiently Securing Systems from Code Reuse Attacks. IEEE Trans. Computers 63(5): 1144-1156 (2014) - [j14]Jingjing Wang, Deepak Jagtap, Nael B. Abu-Ghazaleh
Parallel Discrete Event Simulation for Multi-Core Systems: Analysis and Optimization. IEEE Trans. Parallel Distributed Syst. 25(6): 1574-1584 (2014) - [c57]Jesse Elwell, Ryan Riley, Nael B. Abu-Ghazaleh
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks. HPCA 2014: 201-212 - [c56]Karthikeyan Dayalan, Meltem Ozsoy, Dmitry V. Ponomarev:
Dynamic associative caches: Reducing dynamic energy of first level caches. ICCD 2014: 118-124 - [c55]Dmitry Evtyushkin
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution. MICRO 2014: 190-202 - [c54]Yi Zhang, Jingjing Wang, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh
Exploring many-core architecture design space for parallel discrete event simulation. SIGSIM-PADS 2014: 95-104 - 2013
- [c53]Mehmet Kayaalp, Timothy Schmitt, Junaid Nomani, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
SCRAP: Architecture for signature-based protection from Code Reuse Attacks. HPCA 2013: 258-269 - [c52]Alexey Baranov, Peter Panfilov
PowerVisor: A Toolset for Visualizing Energy Consumption and Heat Dissipation Processes in Modern Processor Architectures. PaCT 2013: 149-153 - [c51]Jingjing Wang, Ketan Bahulkar, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
Can PDES scale in environments with heterogeneous delays? SIGSIM-PADS 2013: 35-46 - [c50]Jingjing Wang, Nael B. Abu-Ghazaleh
Interference resilient PDES on multi-core systems: towards proportional slowdown. SIGSIM-PADS 2013: 115-126 - [p1]Gürhan Küçük, Isa Ahmet Güney
Instruction Scheduling in Microprocessors. Automated Scheduling and Planning 2013: 39-60 - 2012
- [j13]Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael B. Abu-Ghazaleh
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks. ACM Trans. Archit. Code Optim. 8(4): 35:1-35:21 (2012) - [c49]Dmitry Ponomarev
Tensor model of IMS network. ICUMT 2012: 56-62 - [c48]Deepak Jagtap, Nael B. Abu-Ghazaleh
Optimization of Parallel Discrete Event Simulator for Multi-core Systems. IPDPS 2012: 520-531 - [c47]Mehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh
Branch regulation: Low-overhead protection from code reuse attacks. ISCA 2012: 94-105 - [c46]Deepak Jagtap, Ketan Bahulkar, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh
Characterizing and Understanding PDES Behavior on Tilera Architecture. PADS 2012: 53-62 - [c45]Jingjing Wang, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh
Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters. PADS 2012: 93-95 - [c44]Ketan Bahulkar, Jingjing Wang, Nael B. Abu-Ghazaleh
Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation. PADS 2012: 221-230 - 2011
- [c43]Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden:
Mathematical limits of parallel computation for embedded systems. ASP-DAC 2011: 653-660 - [c42]Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. Conf. Computing Frontiers 2011: 37 - [c41]Jared Schmitz, Jason Loew, Jesse Elwell, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
TPM-SIM: a framework for performance evaluation of trusted platform modules. DAC 2011: 236-241 - [c40]Dmitry Evtyushkin
CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors. PaCT 2011: 284-289 - 2010
- [c39]Ketan Bahulkar, Nicole Hofmann, Deepak Jagtap, Nael B. Abu-Ghazaleh
Performance Evaluation of PDES on Multi-core Clusters. DS-RT 2010: 131-140 - [c38]Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden:
A co-processor approach for accelerating data-structure intensive algorithms. ICCD 2010: 431-438 - [c37]Leonid Domnitser, Nael B. Abu-Ghazaleh
A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors. MMM-ACNS 2010: 70-85 - [c36]Jason Loew, Dmitry Ponomarev, Patrick H. Madden:
Customized architectures for faster route finding in GPS-based navigation systems. SASP 2010: 36-43
2000 – 2009
- 2009
- [j12]Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry Ponomarev:
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches. SIGARCH Comput. Archit. News 37(2): 2-9 (2009) - [c35]Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev:
MPTLsim: a simulator for X86 multicore processors. DAC 2009: 226-231 - [c34]Hui Zeng, Kanad Ghose, Dmitry Ponomarev:
Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures. ICPP 2009: 453-461 - [c33]Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev:
Energy-efficient renaming with register versioning. ISLPED 2009: 171-176 - 2008
- [j11]Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev:
Reducing register pressure in SMT processors through L2-miss-driven early register release. ACM Trans. Archit. Code Optim. 5(3): 13:1-13:28 (2008) - [j10]Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose:
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. IEEE Trans. Computers 57(1): 82-95 (2008) - [j9]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective Writeback: Reducing Register File Pressure and Energy Consumption. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 650-661 (2008) - [c32]Jason Loew, Dmitry Ponomarev:
Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures. ICPP 2008: 182-189 - [c31]Balaji Vijayn
Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures. SBAC-PAD 2008: 3-10 - [c30]Jason Loew, Dmitry Ponomarev:
Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? SBAC-PAD 2008: 11-18 - [c29]Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev:
Hiding Communication Delays in Clustered Microarchitectures. SBAC-PAD 2008: 107-114 - 2007
- [j8]Joseph J. Sharkey, Dmitry V. Ponomarev:
Exploiting Operand Availability for Efficient Simultaneous Multithreading. IEEE Trans. Computers 56(2): 208-223 (2007) - [c28]Joseph J. Sharkey, Dmitry V. Ponomarev:
An L2-miss-driven early register deallocation for SMT processors. ICS 2007: 138-147 - 2006
- [j7]Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
Instruction packing: Toward fast and energy-efficient instruction scheduling. ACM Trans. Archit. Code Optim. 3(2): 156-181 (2006) - [j6]Dmitry V. Ponomarev, Gurhan Kucuk
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. IEEE Trans. Computers 55(2): 199-213 (2006) - [j5]Oguz Ergin
Early Register Deallocation Mechanisms Using Checkpointed Register Files. IEEE Trans. Computers 55(9): 1153-1166 (2006) - [c27]Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev:
Adaptive reorder buffers for SMT processors. PACT 2006: 244-253 - [c26]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. PACT 2006: 265-274 - [c25]Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal:
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. HiPC 2006: 135-147 - [c24]Joseph J. Sharkey, Dmitry V. Ponomarev:
Efficient instruction schedulers for SMT processors. HPCA 2006: 288-298 - [c23]Joseph J. Sharkey, Dmitry Ponomarev:
Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. ICPP 2006: 329-336 - [c22]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal:
Address-Value Decoupling for Early Register Deallocation. ICPP 2006: 337-346 - [c21]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective writeback: exploiting transient values for energy-efficiency and performance. ISLPED 2006: 37-42 - 2005
- [c20]Joseph J. Sharkey, Dmitry V. Ponomarev:
Non-uniform Instruction Scheduling. Euro-Par 2005: 540-549 - [c19]Joseph J. Sharkey, Dmitry V. Ponomarev:
Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. Euro-Par 2005: 550-559 - [c18]Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
Power-Efficient Wakeup Tag Broadcast. ICCD 2005: 654-661 - [c17]Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin:
Instruction packing: reducing power and delay of the dynamic scheduling logic. ISLPED 2005: 30-35 - 2004
- [j4]Gurhan Kucuk
Complexity-Effective Reorder Buffer Designs for Superscalar Processors. IEEE Trans. Computers 53(6): 653-665 (2004) - [j3]Dmitry V. Ponomarev, Gurhan Kucuk
Isolating Short-Lived Operands for Energy Reduction. IEEE Trans. Computers 53(6): 697-709 (2004) - [j2]Dmitry V. Ponomarev, Gurhan Kucuk
Energy Efficient Comparators for Superscalar Datapaths. IEEE Trans. Computers 53(7): 892-904 (2004) - [c16]Oguz Ergin
Increasing Processor Performance Through Early Register Release. ICCD 2004: 480-487 - [c15]Oguz Ergin
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. MICRO 2004: 304-315 - [c14]Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. PACS 2004: 15-29 - 2003
- [j1]Dmitry V. Ponomarev, Gurhan Kucuk
Energy-efficient issue queue design. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 789-800 (2003) - [c13]Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin
Reducing Datapath Energy through the Isolation of Short-Lived Operands. IEEE PACT 2003: 258-268 - [c12]Gurhan Kucuk, Oguz Ergin
Distributed Reorder Buffer Schemes for Low Power. ICCD 2003: 364-370 - [c11]Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin
Reducing reorder buffer complexity through selective operand caching. ISLPED 2003: 235-240 - [c10]Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin
Power efficient comparators for long arguments in superscalar processors. ISLPED 2003: 378-383 - [c9]Gurhan Kucuk, Oguz Ergin
Energy Efficient Register Renaming. PATMOS 2003: 219-228 - 2002
- [c8]Dmitry Ponomarev, Gurhan Kucuk
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. DATE 2002: 124-129 - [c7]Oguz Ergin
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. ICCD 2002: 118-121 - [c6]Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose:
Low-complexity reorder buffer architecture. ICS 2002: 57-66 - [c5]Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
Energy-Efficient Design of the Reorder Buffer. PATMOS 2002: 289-299 - 2001
- [c4]Dmitry Ponomarev, Kanad Ghose, Evgeny Saksonov
Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters. Euro-Par 2001: 86-95 - [c3]Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge:
Energy: efficient instruction dispatch buffer design for superscalar processors. ISLPED 2001: 237-242 - [c2]Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose:
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. MICRO 2001: 90-101
1990 – 1999
- 1998
- [c1]Dmitry V. Ponomarev, Kanad Ghose:
A comparative study of some network subsystem organizations. HiPC 1998: 436-443
Coauthor Index
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