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Peter Lee 0002
Person information
- affiliation: University of Kent
Other persons with the same name
- Peter Lee — disambiguation page
- Peter Lee 0001 — Microsoft Research, USA (and 1 more)
- Peter Lee 0003 — University of Birmingham
- Peter Lee 0004 — University of Oxford
- Peter Lee 0005 — Virginia Tech
- Peter Lee 0006 (aka: Peter John Lee) — University of the Arts London, UK
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2010 – 2019
- 2015
- [j7]Jean-Jacques Vandenbussche, Peter Lee, Joan Peuteman:
Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays. IET Signal Process. 9(5): 449-456 (2015) - [j6]Mandeep Chaudhary, Peter Lee:
An Improved Two-Step Binary Logarithmic Converter for FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 476-480 (2015) - 2014
- [j5]Mandeep Chaudhary, Peter Lee:
Two-stage logarithmic converter with reduced memory requirements. IET Comput. Digit. Tech. 8(1): 23-29 (2014) - [j4]Jean-Jacques Vandenbussche, Peter Lee, Joan Peuteman:
On the Accuracy of Digital Phase Sensitive Detectors Implemented in FPGA Technology. IEEE Trans. Instrum. Meas. 63(8): 1926-1936 (2014) - 2013
- [j3]Jean-Jacques Vandenbussche, Peter Lee, Joan Peuteman:
On the coefficient quantization of Multiplicative FIR filters. Digit. Signal Process. 23(2): 689-700 (2013) - 2011
- [b1]Peter Lee:
Hybrid-logarithmic arithmetic and applications. University of Kent, UK, 2011
2000 – 2009
- 2008
- [c20]James Lloyd Weston, Peter Lee:
FPGA Implementation of Cellular Automata Spaces Using a CAM Based Cellular Architecture. AHS 2008: 315-322 - [c19]Jean-Jacques Vandenbussche, Peter Lee, Joan Peuteman:
Analysis of Time and Frequency Domain Performance of MFIR Filters. ESA 2008: 323-329 - [c18]Peter Lee, Evangelos Alexiadis:
An implementation of a multiplierless Hough transform on an FPGA platform using hybrid-log arithmetic. Real-Time Image Processing 2008: 68110G - 2007
- [c17]James Lloyd Weston, Peter Lee:
Cellular Automata Based Binary Arithmetic for use on Self Repairing, Fault Tolerant Hardware. AHS 2007: 732-739 - [c16]Michael Wisdom, Peter Lee:
An Efficient Implementation of a 2D DWT on FPGA. FPL 2007: 222-227 - [c15]Michael Wisdom, Peter Lee:
Evaluation of a Hybrid-Log 2D Wavelet Image Transform. DSP 2007: 411-414 - [c14]James Lloyd Weston, Peter Lee:
An Unbounded Parallel Binary Tree Adder for use on a Cellular Platform. ALIFE 2007: 386-393 - [c13]Peter Lee, Esther Costa, Stephanie McBader, Luca Clementel, Alvise Sartori:
LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric. IJCNN 2007: 2764-2769 - [c12]Charan Litchfield, Peter Lee, Richard J. Langley, John C. Batchelor:
Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels. ISCAS 2007: 3526-3529 - 2006
- [j2]Robert M. Carter, Yong Yan
, Peter Lee:
On-line Nonintrusive Measurement of Particle Size Distribution Through Digital Imaging. IEEE Trans. Instrum. Meas. 55(6): 2034-2038 (2006) - [j1]Yong Yan
Mass Flow Measurement of Fine Particles in a Pneumatic Suspension Using Electrostatic Sensing and Neural Network Techniques. IEEE Trans. Instrum. Meas. 55(6): 2330-2334 (2006) - 2005
- [c11]Charan Litchfield, Richard J. Langley, Peter Lee, John C. Batchelor:
Least squares adaptive algorithms suitable for multiplierless LMMSE detection in 3rd generation mobile systems. PIMRC 2005: 1039-1044 - [c10]Charan Litchfield, Richard J. Langley, Peter Lee, John C. Batchelor
The use of hybrid logarithmic arithmetic for root raised cosine matched filters in WCDMA downlink receivers. WCNC 2005: 596-600 - 2003
- [c9]Stavros Paschalakis, Peter Lee, Miroslaw Bober:
An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. FPL 2003: 543-552 - [c8]Stavros Paschalakis, Peter Lee:
Double precision floating-point arithmetic on FPGAs. FPT 2003: 352-358 - [c7]Stephanie McBader, Peter Lee:
An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems. IPDPS 2003: 228 - 2002
- [c6]Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee:
SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. FPL 2002: 1084-1087 - [c5]Stephanie McBader, Peter Lee:
A programmable image signal processing architecture for embedded vision systems. DSP 2002: 1269-1272 - 2000
- [c4]Stavros Paschalakis, Peter Lee:
Combined Geometric Transformation and Illumination Invariant Object Recognition in RGB Color Images. ICPR 2000: 3588-3591 - [c3]Stavros Paschalakis, Peter Lee:
Statistical Pattern Recognition Using the Normalized Complex Moment Components Vector. SSPR/SPR 2000: 532-539
1990 – 1999
- 1998
- [c2]Ali Zakerolhosseini, Peter Lee, Ed Horne:
An FPFA Based Object Recognition Machine. FPL 1998: 228-237 - 1995
- [c1]Roberto Battiti, Peter Lee, Alvise Sartori, Giampietro Tecchiolli:
Special-purpose parallel architectures for high-performance machine learning. HPCN Europe 1995: 944
Coauthor Index
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