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Stephen A. Szygenda
Person information
- affiliation: Southern Methodist University, Dallas, Texas, USA
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2010 – 2019
- 2014
- [c34]Mitchell A. Thornton
, Theodore W. Manikas
System Probability Distribution Modeling Using MDDs. ISMVL 2014: 196-201
2000 – 2009
- 2008
- [j14]Chad M. Lawler, Michael A. Harper, Stephen A. Szygenda, Mitchell A. Thornton
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility. Int. J. Bus. Inf. Syst. 3(3): 317-331 (2008) - [j13]Gerard Ibarra, Jerrell T. Stracener, Stephen A. Szygenda:
A Systems Engineering Approach for Identifying the Most Critical Links of a Highway System: A Framework Consisting of a Methodology and Mathematical Model. IEEE Syst. J. 2(2): 198-208 (2008) - 2004
- [c33]Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda:
Test vector generation and classification using FSM traversals. ISCAS (5) 2004: 309-312 - [c32]Lun Li, Mitchell A. Thornton, Stephen A. Szygenda:
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. ISVLSI 2004: 32-38 - 2003
- [j12]Sungho Kang, Stephen A. Szygenda:
Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. Simul. 79(2): 59-68 (2003)
1990 – 1999
- 1997
- [c31]Saghir A. Shaikh, Stephen A. Szygenda:
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. Annual Simulation Symposium 1997: 64-74 - [c30]Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, Dominik Kacprzak, Stephen A. Szygenda:
Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. Annual Simulation Symposium 1997: 168-176 - [c29]Charles Wiley, A. T. Campbell III, Stephen A. Szygenda, Donald S. Fussell, Fred Hudson:
Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects. Graphics Interface 1997: 88-96 - 1996
- [j11]E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott:
An Integrated Hardware Array for Very High Speed Logic Simulation. VLSI Design 4(2): 107-118 (1996) - [j10]Sungho Kang, Youngmin Hur, Stephen A. Szygenda:
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. VLSI Design 4(2): 119-133 (1996) - [c28]Youngmin Hur, Stephen A. Szygenda:
A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. Annual Simulation Symposium 1996: 212-220 - [c27]Youngmin Hur, Stephen A. Szygenda:
A Graphical Simulation and Automatic Model Generation System. ESM 1996: 278-282 - [c26]Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda:
CON2FERS: A Concurrent Concurrent Fault and Design Error Simulator. PDPTA 1996: 109-112 - 1995
- [c25]Youngmin Hur, Stephen A. Szygenda:
Special purpose array processor for digital logic simulation. Annual Simulation Symposium 1995: 297-302 - [c24]Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang:
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. HPCA 1995: 340-347 - [c23]Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda:
Statistics on concurrent fault and design error simulation. ICCD 1995: 622-627 - 1994
- [j9]Sungho Kang, Stephen A. Szygenda:
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. IEEE Des. Test Comput. 11(1): 18-26 (1994) - [j8]Shuchih Ernest Chang, Stephen A. Szygenda:
Automatic Functional Model Generation for Parallel Fault and Design Error Simulations. Int. J. Artif. Intell. Tools 3(2): 127-156 (1994) - [j7]Sungho Kang, Stephen A. Szygenda:
Automatic Simulator Generation System. Simul. 63(6): 360-368 (1994) - [j6]Sungho Kang, Stephen A. Szygenda:
The simulation automation system (SAS); concepts, implementation, and results. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 89-99 (1994) - 1993
- [c22]Sungho Kang, Stephen A. Szygenda:
Automatic VHDL Model Generation System. CHDL 1993: 353-360 - [c21]Charles Wiley, K. M. Lau, Stephen A. Szygenda:
m3D: A Multidimensional Dynamic Configurable Router. ISCAS 1993: 1857-1860 - 1992
- [c20]Cheng-I Chuang, Stephen A. Szygenda, James D. Baker:
The automatic element routine generator: an automatic programming tool for functional simulator design. Annual Simulation Symposium 1992: 84-90 - [c19]Sungho Kang, Stephen A. Szygenda:
New design error modeling and metrics for design validation. EURO-DAC 1992: 472-477 - [c18]Sungho Kang, Stephen A. Szygenda:
Modeling and Simulation of Design Errors. ICCD 1992: 443-446 - 1990
- [j5]Jin-Hyeung Kong, Stephen A. Szygenda:
MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach. Comput. Aided Des. 22(10): 618-632 (1990)
1980 – 1989
- 1988
- [c17]Asad Karim, Stephen A. Szygenda:
SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests. IEA/AIE (Vol. 1) 1988: 355-360 - 1987
- [c16]Stephen A. Szygenda, M. Wilson:
Technology transfer: commercializing university research. FJCC 1987: 696-699 - [e7]Stephen A. Szygenda:
Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow. ACM 1987, ISBN 0-8186-0811-0 [contents] - 1982
- [e6]Stephen A. Szygenda, John Hughes, Matt Blanton, Terry J. Wagner, Dennis J. Frailey, Tom Gunter, Chuck McLeavy, G. Jack Lipovski, Miroslaw Malek:
9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982. IEEE Computer Society 1982 [contents]
1970 – 1979
- 1978
- [e5]Stephen A. Szygenda:
Proceedings of the 15th Design Automation Conference, DAC '78, Las Vegas, Nevada, USA, June 19-21, 1978. ACM 1978 [contents] - 1977
- [c15]Ajoy K. Bose, Stephen A. Szygenda:
Design of a diagnosable and fault-tolerant input/output controller. AFIPS National Computer Conference 1977: 795-800 - [c14]Ajoy K. Bose, Stephen A. Szygenda:
Detection of static and dynamic hazards in logic nets. DAC 1977: 220-224 - [e4]Judith G. Brinsfield, Stephen A. Szygenda, David W. Hightower:
Proceedings of the 14th Design Automation Conference, DAC '77, New Orleans, Louisiana, USA, June 20-22, 1977. ACM 1977 [contents] - 1976
- [j4]Stephen A. Szygenda, Edward W. Thompson:
Modeling and Digital Simulation for Design Verification and Diagnosis. IEEE Trans. Computers 25(12): 1242-1253 (1976) - [c13]N. Billawala, Stephen A. Szygenda, Ewald W. Thomson:
A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. ICSE 1976: 151-157 - [e3]Donald J. Humcke, J. Michael Galey, Stephen A. Szygenda, Pat O. Pistilli, Nitta P. Dooner, Judith G. Brinsfield, J. S. Olila:
Proceedings of the 13th Design Automation Conference, DAC '76, San Francisco, California, USA, June 28-30, 1976. ACM 1976 [contents] - 1975
- [j3]Stephen A. Szygenda:
Digital Systems Simulation. Computer 8(3): 23 (1975) - [j2]Stephen A. Szygenda, Edward W. Thompson:
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8(3): 24-36 (1975) - [j1]Edward W. Thompson, Stephen A. Szygenda:
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8(3): 38-49 (1975) - [c12]Edward W. Thompson, Stephen A. Szygenda:
Three levels of accuracy for the simulation of different fault types in digital systems. DAC 1975: 105-113 - [e2]Robert B. Hitchcock Sr., Donald J. Humcke, Stephen A. Szygenda:
Proceedings of the 12th Design Automation Conference, DAC '75, Boston, Massachusetts, USA, June 23-25, 1975. ACM 1975 [contents] - 1974
- [c11]Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce:
Timing analysis for digital fault simulation using assignable delays. DAC 1974: 266-272 - [c10]Stephen A. Szygenda, Anthony A. Lekkos, John L. Fike:
Implemented techniques for handling spikes in an assignable delay simulator. WSC 1974: 721-722 - 1973
- [c9]John L. Fike, Stephen A. Szygenda:
Techniques and modules for element specification in a time - delay logic simulator. ANSS 1973: 276-287 - [c8]Stephen A. Szygenda, Anthony A. Lekkos:
Integrated techniques for functional and gate-level digital logic simulation. DAC 1973: 159-172 - [c7]John M. Hemphill, Stephen A. Szygenda:
Deriving Design Guidelines for Diagnosable Computer Systems. ISCA 1973: 131-135 - [e1]G. Jack Lipovski, Stephen A. Szygenda:
Proceedings of the 1st Annual Symposium on Computer Architecture, Gainesville, FL, USA, December 1973. ACM 1973, ISBN 978-1-4503-7428-6 [contents] - 1972
- [c6]Cliff W. Hemming Jr., Stephen A. Szygenda:
Modular requirements for digital logic simulation at a predefined functional level. ACM Annual Conference (1) 1972: 380-389 - [c5]Stephen A. Szygenda, Edward W. Thompson:
Fault insertion techniques and models for digital logic simulation. AFIPS Fall Joint Computing Conference (2) 1972: 875-884 - [c4]Stephen A. Szygenda:
TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic. DAC 1972: 116-127 - 1971
- [c3]Stephen A. Szygenda, Michael J. Flynn:
Coding techniques for failure recovery in a distributive modular memory organization. AFIPS Spring Joint Computing Conference 1971: 459-466 - [c2]Stephen A. Szygenda, Cliff W. Hemming Jr., John M. Hemphill:
Time flow mechanisms for use in digital logic simulation. WSC 1971: 488-495 - 1970
- [c1]Stephen A. Szygenda, David M. Rouse, Edward W. Thompson:
A model and implementation of a universal time delay simulator for large digital nets. AFIPS Spring Joint Computing Conference 1970: 207-216
Coauthor Index
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