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James Patrick Parkerson
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2010 – 2019
- 2019
- [c11]Haoyan Liu
, Enrique Sanchez, James Patrick Parkerson, Alexander Nelson:
Poster Abstract: Unobtrusive Sleep Monitoring with Low-Cost Pressure Sensor Array. CHASE 2019: 17-18 - [c10]Haoyan Liu
Gesture Classification with Low-Cost Capacitive Sensor Array for Upper Extremity Rehabilitation. IEEE SENSORS 2019: 1-4 - 2018
- [c9]Haoyan Liu
Connected Capacitive Sensor Array for Upper-Extremity Motor Rehabilitation. CHASE 2018: 17-18 - 2015
- [j6]Adam Matthews, Stanislav Bobovych, Nilanjan Banerjee, James Patrick Parkerson, Ryan W. Robucci, Chintan Patel:
Perpetuu: A Tiered Solar-powered GIS Microserver. ACM Trans. Embed. Comput. Syst. 14(4): 78:1-78:21 (2015) - [c8]Stanislav Bobovych, Nilanjan Banerjee, Ryan W. Robucci, James Patrick Parkerson, Jackson Schmandt, Chintan Patel:
SunaPlayer: high-accuracy emulation of solar cells. IPSN 2015: 59-70 - 2014
- [j5]William Johnston, Nilanjan Banerjee, Jackson David Cothren
Information Rich GIS Dissemination in Disconnected Environments. Trans. GIS 18(4): 555-573 (2014) - 2013
- [c7]Alexander Nelson, Jackson Schmandt, William Wilkins, James Patrick Parkerson, Nilanjan Banerjee:
System Support for Micro-Harvester Powered Mobile Sensing. RTSS 2013: 258-267 - 2012
- [c6]Stanislav Bobovych, James Patrick Parkerson, Nilanjan Banerjee:
Evaluating solar panel-driven systems in the laboratory. WiNTECH 2012: 97-98 - 2010
- [j4]Parag K. Lala, Adam Mathews, James Patrick Parkerson:
An Approach for Implementing State Machines with Online Testability. VLSI Design 2010: 639747:1-639747:7 (2010)
2000 – 2009
- 2007
- [j3]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2696-2705 (2007) - 2006
- [j2]Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson:
On self-healing digital system design. Microelectron. J. 37(4): 353-362 (2006) - [j1]Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson:
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2): 406-414 (2006) - 2005
- [c5]C. K. Tang, Parag K. Lala, James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits. ISQED 2005: 128-132 - [c4]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI 2005: 309-310 - 2004
- [c3]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium 2004: 325-330 - [c2]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT 2004: 324-331 - [c1]Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala:
Logic implementation using a reversible gate. Circuits, Signals, and Systems 2004: 452-456
Coauthor Index
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