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S. M. Kang
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Journal Articles
- 2009
- [j8]S. M. Kang, T. I. Shin, Duc V. Dinh, J. H. Yang, Sang-Woo Kim, D. H. Yoon:
Synthesis of GaN nanowires and nanorods via self-growth mode control. Microelectron. J. 40(2): 373-376 (2009) - 2000
- [j7]Y. J. Cho, N. J. Huang, S. M. Kang:
Nonlinear equations for fuzzy mappings in probabilistic normed spaces. Fuzzy Sets Syst. 110(1): 115-122 (2000) - [j6]J. S. Jung, Y. J. Cho, S. M. Kang, B. S. Lee, Y. K. Choi:
Coincidence point theorems in generating spaces of quasi-metric family. Fuzzy Sets Syst. 116(3): 471-479 (2000) - 1999
- [j5]J. S. Jung, S. S. Chang, Y. J. Cho, B. S. Lee, S. M. Kang:
Common fixed point theorems and variational principle in generating spaces of quasi-metric family. Fuzzy Sets Syst. 102(2): 315-325 (1999) - 1998
- [j4]Y. J. Cho, H. K. Pathak, S. M. Kang, J. S. Jung:
Common fixed points of compatible maps of type (β) on fuzzy metric spaces. Fuzzy Sets Syst. 93(1): 99-111 (1998) - 1997
- [j3]S. S. Chang, Y. J. Cho, B. S. Lee, J. S. Jung, S. M. Kang:
Coincidence point theorems and minimization theorems in fuzzy metric spaces. Fuzzy Sets Syst. 88(1): 119-127 (1997) - 1990
- [j2]P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj:
A metal - metal matrix cell generator for multi-level metal MOS technology. Integr. 9(1): 25-47 (1990) - 1988
- [j1]Wei Shu, Min-You Wu, S. M. Kang:
Improved net merging method for gate matrix layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 947-951 (1988)
Conference and Workshop Papers
- 1999
- [c10]U. Ekambaram, S. M. Kang, R. A. Saleh:
Behavioral-level envelope-following using Broyden's method. ICECS 1999: 1437-1440 - 1997
- [c9]A. Dharchoudhuri, S. M. Kang:
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects. VLSI Design 1997: 111-117 - 1993
- [c8]Dae-Hyung Cho, S. M. Kang:
An Accurate AC Characteristic Table Look-up Model for VLSI Analog Circuits Simulation Applications. ISCAS 1993: 1531-1534 - 1992
- [c7]Abhijit Dharchoudhury, S. M. Kang:
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. VLSI Design 1992: 339-340 - 1991
- [c6]Philippe Duchene, Michel J. Declercq, S. M. Kang:
An integrated layout system for sea-of-gates module generation. EURO-DAC 1991: 237-241 - 1989
- [c5]Andrew T. Yang, S. M. Kang:
iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development. DAC 1989: 630-633 - [c4]Y.-H. Shih, S. M. Kang:
Fast MOS circuit simulation with a direct equation solver. ICCD 1989: 276-279 - 1988
- [c3]D. Zhou, Franco P. Preparata, S. M. Kang:
Interconnection delay in very high-speed VLSI. ICCD 1988: 52-55 - [c2]Andrew T. Yang, D. S. Gao, S. M. Kang:
Computer-aided simulation of optical interconnects for high-speed digital systems. ICCD 1988: 87-90 - 1986
- [c1]R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby:
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning. DAC 1986: 418-424
Parts in Books or Collections
- 1993
- [p1]S. M. Kang, M. Sriram:
Binary formulations for Placement and Routing Problems. Algorithmic Aspects of VLSI Layout 1993: 25-68
Coauthor Index
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