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Gabriele Serra
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2020 – today
- 2024
- [j4]Vahid Eftekhari Moghadam
, Gabriele Serra
Memory Integrity Techniques for Memory-Unsafe Languages: A Survey. IEEE Access 12: 43201-43221 (2024) - 2023
- [j3]Sandro Di Leonardi
Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints. IEEE Access 11: 35591-35607 (2023) - [c8]Gabriele Serra, Pietro Fara, Daniel Casini:
Enhancing the Availability of Web Services in the IoT-to-Edge-to-Cloud Compute Continuum: A WordPress Case Study. DSD 2023: 602-609 - [c7]Pietro Fara, Gabriele Serra, Federico Aromolo:
Bounded transmission latency in real-time edge computing: a scheduling analysis. DSD 2023: 618-625 - 2022
- [c6]Gabriele Serra
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms. RTAS 2022: 241-253 - 2021
- [j2]Gabriele Serra, Gabriele Ara, Pietro Fara, Tommaso Cucinotta:
ReTiF: A declarative real-time scheduling framework for POSIX systems. J. Syst. Archit. 118: 102210 (2021) - [c5]Pietro Fara, Gabriele Serra
Scheduling Replica Voting in Fixed-Priority Real-Time Systems. ECRTS 2021: 13:1-13:21 - 2020
- [c4]Gabriele Serra, Gabriele Ara, Pietro Fara, Tommaso Cucinotta:
An Architecture for Declarative Real-Time Scheduling on Linux. ISORC 2020: 20-28
2010 – 2019
- 2019
- [c3]Ciro Donnarumma, Pietro Fara
EN-50128 Certification-Oriented Design of a Safety-Critical Hard Real-Time Kernel. ISSRE Workshops 2019: 314-317
2000 – 2009
- 2007
- [j1]Andrea Balluchi, Antonio Bicchi, Emanuele Mazzi, Alberto L. Sangiovanni-Vincentelli, Gabriele Serra:
Hybrid modelling and control of the common rail injection system. Int. J. Control 80(11): 1780-1795 (2007) - 2006
- [c2]Andrea Balluchi, Antonio Bicchi, Emanuele Mazzi, Alberto L. Sangiovanni-Vincentelli
Hybrid Modelling and Control of the Common Rail Injection System. HSCC 2006: 79-92 - 2002
- [c1]Giovanni Fiengo, Luigi Glielmo
Control oriented models for TWC-equipped spark ignition engines during the warm-up phase. ACC 2002: 1761-1766
Coauthor Index
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