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N. Prasad 0001
Person information
- affiliation: Indian Institute of Technology, Kharagpur, India
Other persons with the same name
- N. Prasad 0002 — Computer Applications, New York, NY, USA
- N. Prasad 0003 (aka: Narayan Prasad R.) — Texas A&M University, College Station, TX, USA
- N. Prasad 0004 — Shri Vishnu Engineering College for Women, Bhimavaram, India
- N. Prasad 0005 — Aarhus University, Herning, Denmark
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2020 – today
- 2021
- [j6]Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay:
Embedding delay-based physical unclonable functions in networks-on-chip. IET Circuits Devices Syst. 15(1): 27-41 (2021)
2010 – 2019
- 2019
- [i1]N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti:
Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. CoRR abs/1908.00289 (2019) - 2018
- [j5]N. Prasad
, Priyajit Mukherjee, Santanu Chattopadhyay, Indrajit Chakrabarti:
Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distributed Comput. 113: 17-36 (2018) - [j4]Vikash Sehwag, N. Prasad
A Parallel Stochastic Number Generator With Bit Permutation Networks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 231-235 (2018) - [j3]N. Prasad
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3543-3554 (2018) - 2017
- [c5]N. Prasad
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS 2017: 1-4 - [c4]Rajit Karmakar, N. Prasad
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSID 2017: 429-434 - 2016
- [c3]Avishek Sinha Roy, N. Prasad
Approximate conditional carry adder for error tolerant applications. VDAT 2016: 1-6 - 2015
- [j2]Abhishek Mankar, N. Prasad
Multiplier-less VLSI architectures for radix-22 folded pipelined complex FFT core. Int. J. Circuit Theory Appl. 43(11): 1743-1758 (2015) - [j1]N. Prasad
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. Microprocess. Microsystems 39(8): 741-751 (2015) - [c2]N. Prasad
ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. iNIS 2015: 146-151 - 2014
- [c1]Navonil Chatterjee
A spare link based reliable Network-on-Chip design. VDAT 2014: 1-6
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