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Hae-Wook Choi
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2010 – 2019
- 2014
- [c13]Hae Young Rha, Byoung Gu Jeon, Hae-Wook Choi:
Efficient guard interval reduction for coherent optical OFDM. OFC 2014: 1-3 - [c12]Thu Phuong Nguyen, Minh-Tuan Le, Vu-Duc Ngo
, Xuan-Nam Tran
Spatial Modulation for High-Rate Transmission Systems. VTC Spring 2014: 1-5 - 2010
- [j5]Hun-sik Kang, Min-Lee Hwang, Jin Lee, Sok-Kyu Lee, Hae-Wook Choi, Sin-Chong Park:
A Calibration Scheme for Delay Mismatch Compensation in OFDM-Based Polar Transmitter. IEICE Trans. Commun. 93-B(10): 2791-2794 (2010)
2000 – 2009
- 2007
- [c11]Seongmin Noh, Daehyun Kim, Vu-Duc Ngo
Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip. ISPA 2007: 268-277 - [c10]Huy Nam Nguyen, Vu-Duc Ngo
An QoS Aware Mapping of Cores Onto NoC Architectures. ISPA 2007: 278-288 - [c9]Vu-Duc Ngo
Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling. ISPA 2007: 289-302 - 2006
- [j4]Jungbo Son, Hae-Wook Choi, Sin-Chong Park:
Accelerating Verification with Reusable Testbench. IEICE Trans. Inf. Syst. 89-D(2): 853-856 (2006) - [j3]Sang-Ho Seo, Hae-Wook Choi, Sin-Chong Park:
Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method. IEICE Trans. Commun. 89-B(4): 1413-1416 (2006) - [j2]Ho-Seok Choi, Hae-Wook Choi, Sin-Chong Park:
Instruction Based Synthesizable Testbench Architecture. IEICE Trans. Electron. 89-C(5): 653-657 (2006) - [c8]Vu-Duc Ngo
The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. ISPA 2006: 75-85 - [c7]Vu-Duc Ngo
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. ISPA Workshops 2006: 791-802 - 2005
- [c6]Vu-Duc Ngo
Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. EUC 2005: 300-310 - [c5]Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi:
Realization of video object plane decoder on mesh on-chip network architecture. Circuits, Signals, and Systems 2005: 137-141 - [c4]Huy Nam Nguyen, Vu-Duc Ngo
Realization of Video Object Plane Decoder on On-Chip Network Architecture. ICESS 2005: 256-264 - [c3]Vu-Duc Ngo
Designing On-Chip Network Based on Optimal Latency Criteria. ICESS 2005: 287-298 - 2004
- [c2]Vu-Duc Ngo
An Expurgated Union Bound for Space-Time Code Systems. ICT 2004: 156-162 - [c1]Vu-Duc Ngo, Hae-Wook Choi, Sin-Chong Park:
Expurgated sphere bound for LDPC. PIMRC 2004: 2591-2595
1990 – 1999
- 1995
- [j1]Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak, Bang-Sup Song:
A 10-b 20-Msample/s low-power CMOS ADC. IEEE J. Solid State Circuits 30(5): 514-521 (1995)
Coauthor Index
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