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Carlos Villavieja
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2020 – today
- 2024
- [c8]Akanksha Jain
, Hannah Lin
Limoncello: Prefetchers for Scale. ASPLOS (3) 2024: 577-590 - 2023
- [c7]Padmapriya Duraisamy, Wei Xu, Scott Hare, Ravi Rajwar, David E. Culler, Zhiyi Xu, Jianing Fan, Christopher Kennelly, Bill McCloskey, Danijela Mijailovic, Brian Morris, Chiranjit Mukherjee, Jingliang Ren, Greg Thelen, Paul Turner, Carlos Villavieja, Parthasarathy Ranganathan, Amin Vahdat:
Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale. ASPLOS (3) 2023: 727-741
2010 – 2019
- 2017
- [j3]Victor Garcia, Alejandro Rico, Carlos Villavieja, Paul M. Carpenter
Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors. Int. J. Parallel Program. 45(3): 530-550 (2017) - 2015
- [c6]Marco A. Z. Alves
SiNUCA: A Validated Micro-Architecture Simulator. HPCC/CSS/ICESS 2015: 605-610 - 2013
- [j2]Nikola Rajovic, Lluís Vilanova
The low power architecture approach towards exascale computing. J. Comput. Sci. 4(6): 439-443 (2013) - [c5]Marco A. Z. Alves
Energy Efficient Last Level Caches via Last Read/Write Prediction. SBAC-PAD 2013: 73-80 - 2012
- [j1]Alejandro Rico, Felipe Cabarcas
On the simulation of large-scale architectures using multiple application abstraction levels. ACM Trans. Archit. Code Optim. 8(4): 36:1-36:20 (2012) - [c4]Marco A. Z. Alves
Energy Savings via Dead Sub-Block Prediction. SBAC-PAD 2012: 51-58 - 2011
- [c3]Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. PACT 2011: 340-349 - [c2]Carlos Villavieja, Yoav Etsion, Alex Ramírez, Nacho Navarro:
FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores. Euro-Par (1) 2011: 282-294 - [c1]Nikola Rajovic, Nikola Puzovic, Lluís Vilanova
The low-power architecture approach towards exascale computing. ScalA@SC 2011: 1-2
Coauthor Index
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