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Martin L. Schmatz
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2020 – today
- 2024
- [c19]Agata M. Wijata, Alicja Musial, Dawid Lazaj, Michal Gumiela, Mateusz Przeliorz, Jonas Weiss, Patricia Sagmeister, Thomas Morf, Martin L. Schmatz, Nicolas Longépé, Pierre-Philippe Mathieu, Jakub Nalepa:
Designing (Not Only) Lunar Space Data Centers. IGARSS 2024: 6104-6108 - 2023
- [c18]Michal Gumiela, Alicja Musial, Agata M. Wijata, Dawid Lazaj, Jonas Weiss, Patricia Sagmeister, Thomas Morf, Martin L. Schmatz, Jakub Nalepa:
Benchmarking Space-Based Data Center Architectures. IGARSS 2023: 4970-4973
2010 – 2019
- 2016
- [j14]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
, Christian Menolfi, Matthias Braendli
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits 51(3): 636-648 (2016) - [c17]Navaneeth Rameshan, Robert Birke, Leandro Navarro
Profiling Memory Vulnerability of Big-Data Applications. DSN Workshops 2016: 258-261 - [c16]Robert Birke, Evangelia Kalyvianaki, Walter Binder
Dynamic Block Sizing for Data Stream Processing Systems. IC2E Workshops 2016: 216-222 - 2015
- [c15]Animesh Trivedi
RStore: A Direct-Access DRAM-based Data Store. ICDCS 2015: 674-685 - [c14]Robert Birke, Mathias Björkqvist, Cyriel Minkenberg, Martin L. Schmatz, Lydia Y. Chen:
When Virtual Meets Physical at the Edge: A Field Study on Datacenters' Virtual Traffic. SIGMETRICS 2015: 403-415 - 2014
- [c13]Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. A-SSCC 2014: 89-92 - [c12]Martin L. Schmatz, Rik Jongerius, Gero Dittmann
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation. ICASSP 2014: 7505-7509 - [c11]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC 2014: 378-379 - 2013
- [j13]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits 48(12): 3049-3058 (2013) - [c10]Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC 2013: 468-469 - 2010
- [j12]Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. IEEE J. Solid State Circuits 45(12): 2850-2860 (2010) - [c9]Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ISSCC 2010: 160-161
2000 – 2009
- 2009
- [j11]Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz:
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE J. Solid State Circuits 44(2): 436-449 (2009) - [j10]Lucio Rodoni, George von Büren, Alex Huber, Martin L. Schmatz, Heinz Jäckel:
A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS. IEEE J. Solid State Circuits 44(7): 1927-1941 (2009) - [j9]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz:
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. IEEE J. Solid State Circuits 44(11): 2901-2910 (2009) - 2008
- [j8]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. IEEE J. Solid State Circuits 43(12): 2905-2920 (2008) - [c8]George von Büren, Lucio Rodoni, Heinz Jäckel, Roland Brun, Daniel Holzer, Alex Huber, Martin L. Schmatz:
5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS. ESSCIRC 2008: 166-169 - [c7]Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz:
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. ISSCC 2008: 110-111 - 2007
- [c6]Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. ISSCC 2007: 226-598 - [c5]Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. ISSCC 2007: 446-614 - 2006
- [j7]Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits 41(4): 954-965 (2006) - [j6]Christian Kromer, Gion Sialm, Christian Menolfi, Martin L. Schmatz, Frank Ellinger, Heinz Jäckel:
A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects. IEEE J. Solid State Circuits 41(12): 2921-2929 (2006) - [j5]Thomas Toifl, Martin L. Schmatz, Christian Menolfi:
Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components. IEEE Trans. Commun. 54(9): 1554-1557 (2006) - [c4]Christian Kromer, Gion Sialm, Christian Menolfi, Martin L. Schmatz, Frank Ellinger, Heinz Jäckel:
A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects. ISSCC 2006: 1266-1275 - [c3]Jonas R. M. Weiss, Marcel A. Kossel, Christian Menolfi, Thomas Morf, Martin L. Schmatz, Thomas Toifl, Heinz Jäckel:
A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement. ISSCC 2006: 2082-2091 - [c2]George von Büren, Christian Kromer, Frank Ellinger, Alex Huber, Martin L. Schmatz, Heinz Jäckel:
A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS. ISSCC 2006: 2462-2471 - 2005
- [j4]Christian Kromer, Gion Sialm, Christoph Berger, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni
A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects. IEEE J. Solid State Circuits 40(12): 2667-2679 (2005) - [j3]Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss:
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. IEEE J. Solid State Circuits 40(12): 2700-2712 (2005) - 2004
- [j2]Marcel A. Kossel, Martin L. Schmatz:
Jitter Measurements of High-Speed Serial Links. IEEE Des. Test Comput. 21(6): 536-543 (2004) - [j1]Christian Kromer, Gion Sialm, Thomas Morf, Martin L. Schmatz, Frank Ellinger, Daniel Erni, Heinz Jäckel:
A low-power 20-GHz 52-dBΩ transimpedance amplifier in 80-nm CMOS. IEEE J. Solid State Circuits 39(6): 885-894 (2004) - [c1]Frank Ellinger, Corrado Carta, Lucio Rodoni, George von Büren, David Barras, Martin L. Schmatz, Heinz Jäckel:
BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN. ICT 2004: 891-899
Coauthor Index
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