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Seidai Takeda
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2010 – 2019
- 2012
- [j2]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
:
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2301-2308 (2012) - [c8]Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI 2012: 91-94 - [c7]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI 2012: 233-238 - [c6]Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED 2012: 625-632 - 2011
- [j1]Seidai Takeda, Kyundong Kim, Hiroshi Nakamura
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2499-2509 (2011) - [c5]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - 2010
- [c4]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370
2000 – 2009
- 2009
- [c3]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c2]Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332 - [c1]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617
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