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Koushik K. Das
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2010 – 2019
- 2016
- [c8]Yasuharu Katsuno, Ashish Kundu, Koushik K. Das, Hitomi Takahashi, Robert Schloss, Prasenjit Dey, Mukesh K. Mohania:
Security, Compliance, and Agile Deployment of Personal Identifiable Information Solutions on a Public Cloud. CLOUD 2016: 359-366
2000 – 2009
- 2009
- [c7]Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das:
Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD 2009: 631-636 - 2008
- [j3]Koushik K. Das, Ching-Te Chuang, Richard B. Brown:
Reducing parasitic BJT effects in partially depleted SOI digital logic circuits. Microelectron. J. 39(2): 275-285 (2008) - 2007
- [j2]Koushik K. Das, Steven G. Walker, Manjul Bhushan:
An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability. Proc. IEEE 95(3): 670-687 (2007) - 2006
- [j1]Scott Hanson, Bo Zhai, Kerry Bernstein, David T. Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester:
Ultralow-voltage, minimum-energy CMOS. IBM J. Res. Dev. 50(4-5): 469-490 (2006) - [c6]Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang:
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. VLSI Design 2006: 758-761 - 2004
- [c5]Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang:
Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107 - 2003
- [c4]Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. ESSCIRC 2003: 309-312 - [c3]Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171 - [c2]Koushik K. Das, Richard B. Brown:
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. ISVLSI 2003: 29-34 - [c1]Koushik K. Das, Richard B. Brown:
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. VLSI Design 2003: 291-296
Coauthor Index
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