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Yongsam Moon
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2010 – 2019
- 2016
- [j10]Yongsam Moon:
Signal detector for 6-Gbps 55-nm CMOS Serial ATA receiver. IEICE Electron. Express 13(9): 20160286 (2016) - 2012
- [j9]Seon-Woo Hwang, Yongsam Moon:
Divide-by-N and divide-by-N/N+1 prescalers based on a shift register and a multi-input NOR gate. IEICE Electron. Express 9(20): 1611-1616 (2012) - 2010
- [j8]Yongsam Moon:
A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver. IEICE Electron. Express 7(13): 931-935 (2010)
2000 – 2009
- 2009
- [j7]Yongsam Moon:
TX rise/fall time control for multi-rate serial link. IEICE Electron. Express 6(5): 244-248 (2009) - [c4]Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim:
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. ISSCC 2009: 128-129 - 2008
- [c3]Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun:
Presetting pulse-based flip-flop. ISCAS 2008: 588-591 - 2006
- [c2]Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim:
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. ISSCC 2006: 233-242 - 2005
- [j6]Yongsam Moon, Sang-Hyun Lee, Daeyun Shim:
A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS. IEEE J. Solid State Circuits 40(5): 1175-1179 (2005) - 2004
- [j5]Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong:
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits 39(5): 795-803 (2004) - 2002
- [j4]Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn:
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. IEEE J. Solid State Circuits 37(12): 1822-1830 (2002) - 2001
- [j3]Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn:
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. IEEE J. Solid State Circuits 36(12): 1974-1983 (2001) - 2000
- [j2]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits 35(3): 377-384 (2000)
1990 – 1999
- 1999
- [c1]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC 1999: 299-302 - 1997
- [j1]Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim:
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits 32(5): 691-700 (1997)
Coauthor Index
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