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Ivan Beretta
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2010 – 2019
- 2016
- [j7]Vincenzo Rana
, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto:
Efficient Hardware Design of Iterative Stencil Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2018-2031 (2016) - [j6]Ivan Beretta, Vincenzo Rana
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices. ACM Trans. Embed. Comput. Syst. 15(3): 44:1-44:27 (2016) - 2015
- [c14]Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL 2015: 1-8 - 2014
- [j5]Rubén Braojos, Ivan Beretta, Giovanni Ansaloni, David Atienza
Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes. Sensors 14(12): 22532-22551 (2014) - [j4]Juan Antonio Clemente
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms. ACM Trans. Reconfigurable Technol. Syst. 7(2): 9:1-9:27 (2014) - [c13]Rubén Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza:
Hardware/software approach for code synchronization in low-power multi-core sensor nodes. DATE 2014: 1-6 - [c12]Rubén Braojos, Ivan Beretta, Jeremy Constantin, Andreas Peter Burg
A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead. EUC 2014: 265-272 - 2013
- [j3]Vincenzo Rana
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms. IEEE Des. Test 30(4): 71-80 (2013) - [c11]Alessandro Antonio Nacci, Vincenzo Rana
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. DAC 2013: 52:1-52:6 - 2012
- [c10]Paolo Roberto Grassi, Vincenzo Rana
B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks. BSN 2012: 46-51 - [c9]Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana
Knowledge-based design space exploration of wireless sensor networks. CODES+ISSS 2012: 225-234 - [c8]Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana
Design exploration of energy-performance trade-offs for wireless sensor networks. DAC 2012: 1043-1048 - [c7]Paolo Roberto Grassi, Vincenzo Rana
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks. DSD 2012: 874-881 - [c6]Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana
Model-based design for wireless body sensor network nodes. LATW 2012: 1-6 - 2011
- [j2]Ivan Beretta, Vincenzo Rana
Island-Based Adaptable Embedded System Design. IEEE Embed. Syst. Lett. 3(2): 53-57 (2011) - [j1]Ivan Beretta, Vincenzo Rana
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1211-1224 (2011) - [c5]Abdulkadir Akin, Ivan Beretta, A. A. Nacci, Vincenzo Rana, Marco D. Santambrogio, David Atienza:
A high-performance parallel implementation of the Chambolle algorithm. DATE 2011: 1436-1441 - [c4]Juan Antonio Clemente
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware. FPL 2011: 177-180 - 2010
- [c3]Marco D. Santambrogio
Operating system runtime management of partially dynamically reconfigurable embedded systems. ESTIMedia 2010: 1-10 - [c2]Ivan Beretta, Vincenzo Rana
Run-time mapping of applications on FPGA-based reconfigurable systems. ISCAS 2010: 3329-3332
2000 – 2009
- 2009
- [c1]Ivan Beretta, Vincenzo Rana
On-line task management for a reconfigurable cryptographic architecture. IPDPS 2009: 1-4
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