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Bogong Su
Person information
- affiliation: William Paterson University, Department of Computer Science, Wayne, NJ, USA
- affiliation (1991 - 1994): City University of New York, College of Staten Island, NY, USA
- affiliation (PhD 1993): Tsinghua University, Department of Computer Science and Technology, Beijing, China
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2020 – today
- 2021
- [j8]Weihua Liu
, Erh-Wen Hu, Bogong Su, Jian Wang:
Using machine learning techniques for DSP software performance prediction at source code level. Connect. Sci. 33(1): 26-41 (2021) - 2020
- [c25]Oliver Alvarado Rodriguez, Dev Dave, Weihua Liu, Bogong Su:
A Study of Machine Learning Inference Benchmarks. ICAIP 2020: 167-171
2010 – 2019
- 2019
- [j7]Erh-Wen Hu, Weihua Liu, Bogong Su, Jian Wang:
Comparing DSP Software Performance Prediction Models at Source Code Level - From Analytical to Statistical. J. Softw. 14(6): 247-256 (2019) - 2017
- [c24]Erh-Wen Hu, Bogong Su, Jian Wang:
Software performance prediction at source level. SERA 2017: 263-270
2000 – 2009
- 2006
- [c23]Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang:
New DSP Benchmark based on Selectable Mode Vocoder (SMV). CDES 2006: 175-181 - 2004
- [c22]Bogong Su, Jian Wang, Rafi Rabipour, Erh-Wen Hu, Joseph B. Manzano:
Loop optimization with tradeoff between cycle count and code size for DSP applications. EUSIPCO 2004: 1357-1360 - [c21]Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano:
Software De-Pipelining Technique. SCAM 2004: 7-16 - 2003
- [c20]Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano:
De-pipeline a software-pipelined loop. ICASSP (2) 2003: 237-240 - 2000
- [c19]Jian Wang, Bogong Su, Erh-Wen Hu:
A scalable loop optimization approach for scalable DSP processors. ICASSP 2000: 3646-3649
1990 – 1999
- 1999
- [c18]Bogong Su, Jian Wang, Andrew Esguerra:
Source-level loop optimization for DSP code generation. ICASSP 1999: 2155-2158 - 1998
- [j6]Vicki H. Allan, Steven J. Beaty, Bogong Su, Philip H. Sweany:
Building a Retargetable Local Instruction Scheduler. Softw. Pract. Exp. 28(3): 249-283 (1998) - [c17]Jian Wang, Bogong Su:
Software pipelining of nested loops for real-time DSP applications. ICASSP 1998: 3065-3068 - 1994
- [j5]Jian Wang, Christine Eisenbeis, Martin Jourdan, Bogong Su:
Decomposed software pipelining: A new perspective and a new approach. Int. J. Parallel Program. 22(3): 351-373 (1994) - [j4]Jian Wang, Christine Eisenbeis, Bogong Su:
Using timed Petri net to model instruction-level loop scheduling with resource constraints. J. Comput. Sci. Technol. 9(2): 128-143 (1994) - [c16]Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu:
A study of pointer aliasing for software pipelining using run-time disambiguation. MICRO 1994: 112-117 - 1993
- [j3]Bogong Su, Jian Wang, Zhizhong Tang, Chihong Zhang, Wei Zhao:
URPR-1: A single-chip VLIW architecture. Microprocess. Microprogramming 39(1): 25-41 (1993) - [c15]Zhizhong Tang, Gang Chen, Chihong Zhang, Yingwei Zhang, Bogong Su, Stanley Habib:
GPMB - software pipelining branch-intensive loops. MICRO 1993: 21-30 - 1992
- [j2]Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang:
Foresighted Instruction Scheduling Under Timing Constraints. IEEE Trans. Computers 41(9): 1169-1172 (1992) - [c14]Bogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib:
A VLIW architecture for optimal execution of branch-intensive loops. MICRO 1992: 119-124 - 1991
- [c13]Peng Hu, Bogong Su, Chunyi Shi:
Decomposition and allocation of flat-structured problems. COMPSAC 1991: 659-664 - [c12]Bogong Su, Jian Wang:
GURPR*: A New Global Software Pipelining Algorithm. MICRO 1991: 212-216 - 1990
- [c11]Bogong Su, Chunyi Shi, Kehong Wang, Peng Hu, Jiang Wang, Yiming Wu:
Distributed Problem Solving System for Transport Dispatching. IEA/AIE (Vol. 1) 1990: 141-150 - [c10]Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu:
A software pipelining based VLIW architecture and optimizing compiler. MICRO 1990: 17-27
1980 – 1989
- 1988
- [c9]Bogong Su, Chunyi Shi, Kehong Wang, Peng Hu, Hao Shi, Jian Wang:
The Architecture of a Distributed Knowledge Base System. DS-3 1988: 547-556 - [c8]Bogong Su, Jian Wang, Jinshi Xia:
Global microcode compaction under timing constraints. MICRO 1988: 116-118 - 1987
- [c7]Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia:
Microcode compaction with timing constraints. MICRO 1987: 59-68 - [c6]Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia:
GURPR - a method for global software pipelining. MICRO 1987: 88-96 - 1986
- [c5]Bogong Su, Shiyuan Ding, Jinshi Xia:
URPR - An extension of URCR for software pipelining. MICRO 1986: 94-103 - [c4]Robert A. Mueller, Bogong Su, Michael R. Duda, Brian L. Plomondon:
A case study in signal processing microprogramming using the URPR software pipelining technique. MICRO 1986: 104-115 - 1985
- [c3]Bogong Su, Shiyuan Ding:
Some experiments in global microcode compaction. MICRO 1985: 175-180 - 1984
- [c2]Bogong Su, Shiyuan Ding, Lan Jin:
An improvement of trace scheduling for global microcode compaction. MICRO 1984: 78-85 - 1983
- [j1]Ralph Grishman, Bogong Su:
A Preliminary Evaluatin of Trace Scheduling for Global Microcode Compaction. IEEE Trans. Computers 32(12): 1191-1194 (1983) - 1982
- [c1]Bogong Su, Ralph Grishman:
Emulating an MIMD architecture. MICRO 1982: 197-199
Coauthor Index
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