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David Black-Schaffer
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- affiliation: Uppsala Univeristy, Department of Information Technology, Sweden
- affiliation: University of Stanford, Computer Systems Laboratory, CA, USA
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2020 – today
- 2024
- [c49]Jonas Norlinder
, Albert Mingkun Yang
Mutator-Driven Object Placement using Load Barriers. MPLR 2024: 14-27 - 2023
- [j11]Ahmed Nematallah
Exploring the Latency Sensitivity of Cache Replacement Policies. IEEE Comput. Archit. Lett. 22(2): 93-96 (2023) - [c48]Gustaf Borgström
Faster Functional Warming with Cache Merging. DroneSE/RAPIDO@HiPEAC 2023: 39-47 - [c47]Alireza Haddadi
Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping. MEMSYS 2023: 2:1-2:11 - [c46]Muhammad Hassan
Protean: Resource-efficient Instruction Prefetching. MEMSYS 2023: 22:1-22:13 - 2022
- [j10]Rakesh Kumar
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Trans. Archit. Code Optim. 19(2): 25:1-25:28 (2022) - [c45]Chang Hyun Park
Every walk's a hit: making page walks single-access cache hits. ASPLOS 2022: 128-141 - [i2]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. CoRR abs/2201.00485 (2022) - 2021
- [j9]Muhammad Hassan, Chang Hyun Park
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006. ACM Trans. Archit. Code Optim. 18(2): 24:1-24:20 (2021) - [j8]Ricardo Alves, Stefanos Kaxiras, David Black-Schaffer:
Early Address Prediction: Efficient Pipeline Prefetch and Reuse. ACM Trans. Archit. Code Optim. 18(3): 39:1-39:22 (2021) - 2020
- [c44]Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar:
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. HPCA 2020: 424-434 - [c43]Isaac Sánchez Barrera
Modeling and optimizing NUMA effects and prefetching with machine learning. ICS 2020: 34:1-34:13 - [c42]Chang Hyun Park
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages. ISCA 2020: 913-925 - [c41]Muhammad Hassan, Chang Hyun Park, David Black-Schaffer:
Architecturally-Independent and Time-Based Characterization of SPEC CPU 2017. ISPASS 2020: 107-109 - [i1]Chang Hyun Park, Ilias Vougioukas, Andreas Sandberg
Page Tables: Keeping them Flat and Hot (Cached). CoRR abs/2012.05079 (2020)
2010 – 2019
- 2019
- [j7]Mehdi Alipour
Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit. J. Signal Process. Syst. 91(3-4): 379-397 (2019) - [c40]Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer:
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. DATE 2019: 716-721 - [c39]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway: Maximizing MLP for Slice-Out-of-Order Execution. HPCA 2019: 558-569 - [c38]Mihail Popov, Alexandra Jimborean
Efficient thread/page/parallelism autotuning for NUMA systems. ICS 2019: 342-353 - [c37]Ricardo Alves, Alberto Ros
Filter caching for free: the untapped potential of the store-buffer. ISCA 2019: 436-448 - 2018
- [j6]Germán Ceballos
Analyzing performance variation of task schedulers with TaskInsight. Parallel Comput. 75: 11-27 (2018) - [c36]Ricardo Alves, Stefanos Kaxiras, David Black-Schaffer:
Dynamically Disabling Way-prediction to Reduce Instruction Replay. ICCD 2018: 140-143 - [c35]Germán Ceballos, Erik Hagersten, David Black-Schaffer:
Tail-PASS: Resource-Based Cache Management for Tiled Graphics Rendering Hardware. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 55-63 - [c34]Germán Ceballos, Andreas Sembrant, Trevor E. Carlson, David Black-Schaffer:
Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-Based GPUs. ISPASS 2018: 1-11 - 2017
- [j5]Germán Ceballos
Exploring Scheduling Effects on Task Performance with TaskInsight. Supercomput. Front. Innov. 4(3): 91-98 (2017) - [c33]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer:
POSTER: Putting the G back into GPU/CPU Systems Research. PACT 2017: 130-131 - [c32]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations. HPCA 2017: 133-144 - [c31]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer:
A graphics tracing framework for exploring CPU+GPU memory systems. IISWC 2017: 54-65 - [c30]Germán Ceballos, Andreas Sembrant, Trevor E. Carlson, David Black-Schaffer:
Analyzing graphics workloads on tile-based GPUs. IISWC 2017: 108-109 - [c29]Germán Ceballos
Understanding the interplay between task scheduling, memory and performance. SPLASH (Companion Volume) 2017: 21-23 - [c28]Germán Ceballos
TaskInsight: Understanding Task Schedules Effects on Memory and Performance. PMAM@PPoPP 2017: 11-20 - [c27]Gustaf Borgström, Andreas Sembrant, David Black-Schaffer:
Adaptive Cache Warming for Faster Simulations. RAPIDO 2017: 1 - [c26]Ricardo Alves, Nikos Nikoleris, Stefanos Kaxiras, David Black-Schaffer:
Addressing Energy Challenges in Filter Caches. SBAC-PAD 2017: 49-56 - 2016
- [j4]Sam Van den Steen
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Computers 65(12): 3537-3551 (2016) - [c25]Germán Ceballos
Formalizing Data Locality in Task Parallel Applications. ICA3PP Workshops 2016: 43-61 - [c24]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement. ICCD 2016: 117-124 - [c23]Johan Janzen, David Black-Schaffer, Andra Hugo:
Partitioning GPUs for Improved Scalability. SBAC-PAD 2016: 42-49 - 2015
- [c22]Muneeb Khan, Michael A. Laurenzano, Jason Mars, Erik Hagersten, David Black-Schaffer:
AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance. PACT 2015: 367-378 - [c21]Germán Ceballos
StatTask: reuse distance analysis for task-based applications. RAPIDO@HiPEAC 2015: 1:1-1:7 - [c20]Andreas Sandberg
Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed. IISWC 2015: 183-192 - [c19]Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson
Micro-architecture independent analytical processor performance and power modeling. ISPASS 2015: 32-41 - [c18]Andreas Sembrant, Trevor E. Carlson
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO 2015: 334-346 - 2014
- [c17]Alexandra Jimborean
Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling. CGO 2014: 262 - [c16]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Navigating the cache hierarchy with a single lookup. ISCA 2014: 133-144 - 2013
- [c15]David Eklov, Nikos Nikoleris, David Black-Schaffer, Erik Hagersten:
Bandwidth Bandit: Quantitative characterization of memory contention. CGO 2013: 19:1-19:10 - [c14]Andreas Sandberg, Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Modeling performance variation due to cache sharing. HPCA 2013: 155-166 - [c13]Konstantinos Koukos, David Black-Schaffer, Vasileios Spiliopoulos, Stefanos Kaxiras:
Towards more efficient execution: a decoupled access-execute approach. ICS 2013: 253-262 - [c12]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
TLC: a tag-less cache for reducing dynamic first level cache energy. MICRO 2013: 49-61 - 2012
- [c11]Andreas Sandberg
Efficient techniques for predicting cache sharing and throughput. PACT 2012: 305-314 - [c10]David Eklov, Nikos Nikoleris
Bandwidth bandit: quantitative characterization of memory contention. PACT 2012: 457-458 - [c9]Andreas Sembrant, David Black-Schaffer, Erik Hagersten:
Phase guided profiling for fast cache modeling. CGO 2012: 175-185 - [c8]Andreas Sembrant, David Black-Schaffer, Erik Hagersten:
Phase behavior in serial and parallel applications. IISWC 2012: 47-58 - [c7]David Eklov, Nikos Nikoleris
Bandwidth bandit: Understanding memory contention. ISPASS 2012: 116-117 - 2011
- [c6]David Eklov, David Black-Schaffer, Erik Hagersten:
Fast modeling of shared caches in multicore systems. HiPEAC 2011: 147-157 - [c5]David Eklov, Nikos Nikoleris
Cache Pirating: Measuring the Curse of the Shared Cache. ICPP 2011: 165-175 - [c4]Karl Ljungkvist, Martin Tillenius, David Black-Schaffer, Sverker Holmgren, Martin Karlsson, Elisabeth Larsson
Using Hardware Transactional Memory for High-Performance Computing. IPDPS Workshops 2011: 1660-1667 - 2010
- [c3]David Eklov, David Black-Schaffer, Erik Hagersten:
StatCC: a statistical cache contention model. PACT 2010: 551-552 - [c2]David Black-Schaffer, William J. Dally:
Block-Parallel Programming for Real-Time Embedded Applications. ICPP 2010: 297-306
2000 – 2009
- 2008
- [j3]James D. Balfour, William J. Dally, David Black-Schaffer, Vishal Parikh, JongSoo Park:
An Energy-Efficient Processor Architecture for Embedded Systems. IEEE Comput. Archit. Lett. 7(1): 29-32 (2008) - [j2]David Black-Schaffer, James D. Balfour, William J. Dally, Vishal Parikh, JongSoo Park:
Hierarchical Instruction Register Organization. IEEE Comput. Archit. Lett. 7(2): 41-44 (2008) - [j1]William J. Dally, James D. Balfour, David Black-Schaffer, James Chen, R. Curtis Harting, Vishal Parikh, JongSoo Park, David Sheffield:
Efficient Embedded Computing. Computer 41(7): 27-32 (2008) - 2007
- [c1]JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally:
Register pointer architecture for efficient embedded processors. DATE 2007: 600-605
Coauthor Index
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last updated on 2024-10-23 21:26 CEST by the dblp team
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