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Vinay K. Chippa
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2010 – 2019
- 2014
- [j2]Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
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Scalable Effort Hardware Design. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 2004-2016 (2014) - [c9]Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
StoRM: a stochastic recognition and mining processor. ISLPED 2014: 39-44 - 2013
- [j1]Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling. ACM Trans. Embed. Comput. Syst. 12(2s): 90:1-90:23 (2013) - [c8]Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
Approximate computing: An integrated hardware approach. ACSSC 2013: 111-117 - [c7]Vinay K. Chippa, Hrishikesh Jayakumar
Energy-efficient recognition and mining processor using scalable effort design. CICC 2013: 1-4 - [c6]Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
Analysis and characterization of inherent application resilience for approximate computing. DAC 2013: 113:1-113:9 - [c5]Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
Quality programmable vector processors for approximate computing. MICRO 2013: 1-12 - 2011
- [c4]Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608 - [c3]Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy:
Design of voltage-scalable meta-functions for approximate computing. DATE 2011: 950-955 - [c2]Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH 2011: 122-128 - 2010
- [c1]Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560
Coauthor Index
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