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Rajesh Amratlal Thakker
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2020 – today
- 2023
- [j12]Dhara J. Sangani, Rajesh Amratlal Thakker, Sumankumar D. Panchal, Rajesh Gogineni:
Pan-Sharpening for Spectral Details Preservation Via Convolutional Sparse Coding in Non-Subsampled Shearlet Space. Int. J. Image Graph. 23(2): 2350013:1-2350013:24 (2023) - 2021
- [j11]Amit Rathod
, Rajesh Amratlal Thakker:
Parameter extraction of PSP MOSFET model using particle swarm optimisation. Int. J. Comput. Aided Eng. Technol. 14(2): 278-291 (2021) - [j10]Amit Rathod
Accelerating Parameter Extraction of PSP MOSFET Model on SoC Platform. J. Circuits Syst. Comput. 30(13): 2150247:1-2150247:21 (2021)
2010 – 2019
- 2019
- [j9]Manan Mewada, Mazad Zaveri
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. Integr. 69: 381-392 (2019) - [j8]Subhash J. Patel
Parameter Space Exploration for Analog Circuit Design Using Enhanced Bee Colony Algorithm. J. Circuits Syst. Comput. 28(9): 1950153:1-1950153:24 (2019) - [c7]Subhash Jagadishchandra Patel, Rajesh Amratlal Thakker:
Parasitic-Aware Automatic Analog CMOS Circuit Design Environment. VLSID 2019: 245-250 - [i2]Siddhant Bansal
AGDC: Automatic Garbage Detection and Collection. CoRR abs/1908.05849 (2019) - 2018
- [j7]Mitesh Limachia, Rajesh Amratlal Thakker, Nikhil Kothari:
A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology. Integr. 61: 125-137 (2018) - [j6]Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology. Integr. 62: 258-269 (2018) - [c6]Amit Rathod
Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization - SoC Approach. VDAT 2018: 483-494 - [c5]Subhash J. Patel, Rajesh Amratlal Thakker:
Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm. VLSID 2018: 445-446 - 2017
- [c4]Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari
Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology. VLSID 2017: 309-314 - 2015
- [i1]Shailesh Panchal, Rajesh Amratlal Thakker:
Implementation and comparative quantitative assessment of different multispectral image pansharpening approches. CoRR abs/1511.04659 (2015) - 2011
- [j5]Rajesh Amratlal Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao
A novel architecture for improving slew rate in FinFET-based op-amps and OTAs. Microelectron. J. 42(5): 758-765 (2011) - 2010
- [j4]Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Mahesh B. Patil:
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 627-631 (2010) - [c3]Angada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework. ISQED 2010: 713-720
2000 – 2009
- 2009
- [j3]Rajesh Amratlal Thakker, Mahesh B. Patil, K. G. Anil:
Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization. Eng. Appl. Artif. Intell. 22(2): 317-328 (2009) - [j2]Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil:
Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization. J. Low Power Electron. 5(3): 291-302 (2009) - [j1]Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini
A Novel Table-Based Approach for Design of FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1061-1070 (2009) - [c2]Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao
Automated design and optimization of circuits in emerging technologies. ASP-DAC 2009: 504-509 - [c1]Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil:
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization. VLSI Design 2009: 427-432
Coauthor Index
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