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Vladimir Castro Alves
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2020 – today
- 2022
- [j8]Ali Heydarigorji
, Siavash Rezaei
Leveraging Computational Storage for Power-Efficient Distributed Data Analytics. ACM Trans. Embed. Comput. Syst. 21(6): 82:1-82:36 (2022) - [c29]Ali Heydarigorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
In-storage Processing of I/O Intensive Applications on Computational Storage Drives. ISQED 2022: 1-6 - 2021
- [i3]Ali Heydari Gorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
In-storage Processing of I/O Intensive Applications on Computational Storage Drives. CoRR abs/2112.12415 (2021) - 2020
- [j7]Jae Young Do, Victor da Cruz Ferreira, Hossein Bobarshad
Cost-effective, Energy-efficient, and Scalable Storage Computing for Large-scale AI Applications. ACM Trans. Storage 16(4): 21:1-21:37 (2020) - [c28]Ali Heydari Gorji
Stannis: Low-Power Acceleration of DNN Training Using Computational Storage Devices. DAC 2020: 1-6 - [c27]Ali Heydari Gorji, Siavash Rezaei, Mahdi Torabzadehkashi, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
HyperTune: Dynamic Hyperparameter Tuning for Efficient Distribution of DNN Training Over Heterogeneous Systems. ICCAD 2020: 88:1-88:8 - [i2]Ali Heydarigorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
STANNIS: Low-Power Acceleration of Deep Neural Network Training Using Computational Storage. CoRR abs/2002.07215 (2020) - [i1]Ali Heydarigorji, Siavash Rezaei, Mahdi Torabzadehkashi, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
HyperTune: Dynamic Hyperparameter Tuning For Efficient Distribution of DNN Training Over Heterogeneous Systems. CoRR abs/2007.08077 (2020)
2010 – 2019
- 2019
- [j6]Mahdi Torabzadehkashi
Computational storage: an efficient and scalable platform for big data and HPC applications. J. Big Data 6: 100 (2019) - [c26]Mahdi Torabzadehkashi
Accelerating HPC Applications Using Computational Storage Devices. HPCC/SmartCity/DSS 2019: 1878-1885 - [c25]Victor da Cruz Ferreira, Alexandre Solon Nery, Leandro A. J. Marzulo, Leandro Santiago
A Feasible FPGA Weightless Neural Accelerator. ISCAS 2019: 1-5 - [c24]Mahdi Torabzadehkashi
Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics. PDP 2019: 430-437 - 2018
- [c23]Vladimir Castro Alves, Jae Young Do:
MPP 2018 Keynote. IPDPS Workshops 2018: 1231 - [c22]Mahdi Torabzadehkashi
CompStor: An In-storage Computation Platform for Scalable Distributed Processing. IPDPS Workshops 2018: 1260-1267
2000 – 2009
- 2009
- [j5]Ricardo F. Cassia, Vladimir Castro Alves, Federico G.-D. Besnard, Felipe M. G. França
Synchronous-to-Asynchronous Conversion of Cryptographic Circuits. J. Circuits Syst. Comput. 18(2): 271-282 (2009) - 2002
- [c21]José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski, Antonio Carneiro de Mesquita Filho:
Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any Order. LATW 2002: 83-85 - [c20]José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Marcelo Lubaszewski, Vladimir Castro Alves:
State Model Approach for Analog Fault Modeling. LATW 2002: 86-88 - [c19]João M. S. Alcântara, Antônio C. C. Vieira, Federico Gálvez-Durand, Vladimir Castro Alves:
A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions. SBCCI 2002: 149-154 - [c18]Fábio da S. Dutra, Federico Gálvez-Durand, Vladimir Castro Alves:
System on a Chip for Petroleum Pipeline Inspection. SBCCI 2002: 331-336 - [c17]José Vicente Calvano, Vladimir Castro Alves, Antonio Carneiro de Mesquita Filho, Marcelo Lubaszewski:
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. VTS 2002: 201-206 - 2001
- [j4]José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski:
Fault Models and Test Generation for OpAmp Circuits - The FFM. J. Electron. Test. 17(2): 121-138 (2001) - [c16]José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski:
Filter Sensitivity Analysis Using the TRAM. LATW 2001: 80-83 - [c15]José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski, Antonio Carneiro de Mesquita Filho:
Designing Testable Networks for Transfer Function Realization. LATW 2001: 84-87 - 2000
- [j3]Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves:
Design and Implementation of the MorphoSys Reconfigurable Computing Processor. J. VLSI Signal Process. 24(2-3): 147-164 (2000) - [c14]José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. Asian Test Symposium 2000: 96- - [c13]José Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski:
Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method. LATW 2000: 84-87 - [c12]José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
The Use of Macromodels on Op-Amp Circuits Fault Modeling. LATW 2000: 188-192 - [c11]Sergio C. Salomão, João M. S. Alcântara, Vladimir Castro Alves, Felipe M. G. França:
Improved IDEA. SBCCI 2000: 47-54 - [c10]José Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski, Antonio Carneiro de Mesquita Filho:
Fault Models and Compact Test Vectors for MOS OpAmp circuits. SBCCI 2000: 289-294 - [c9]Holger Singpiel, Harald Simmler, Andreas Kugel, Reinhard Männer, Antônio C. C. Vieira, Federico Gálvez-Durand, João M. S. Alcântara, Vladimir Castro Alves:
Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable. SBCCI 2000: 359-364 - [c8]José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. VTS 2000: 319-324
1990 – 1999
- 1999
- [c7]Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi
The MorphoSys Dynamically Reconfigurable System-on-Chip. Evolvable Hardware 1999: 152-160 - [c6]Luiz Maltar, Felipe M. G. França
An FPGA-Based Fan Beam Image Reconstruction Module. FCCM 1999: 312-313 - [c5]João M. S. Alcântara, Sergio C. Salomão, Edson do Prado Granja, Vladimir Castro Alves, Felipe M. G. França:
Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation. VLSI 1999: 173-180 - 1998
- [c4]Vladimir Castro Alves, Felipe M. G. França
A BIST Scheme for Asynchronous Logic. Asian Test Symposium 1998: 27-32 - [c3]Luiz Maltar, Felipe M. G. França
Implementation of RNS Addition and RNS Multiplication into FPGAs. FCCM 1998: 331-332 - 1996
- [c2]Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki:
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. Asian Test Symposium 1996: 263-268 - 1995
- [j2]Michael Nicolaidis, Vladimir Castro Alves, Hakim Bederr:
Testing complex couplings in multiport memories. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 59-71 (1995) - 1994
- [j1]Michael Nicolaidis, O. Kebichi, Vladimir Castro Alves:
Trade-offs in scan path and BIST implementations for RAMs. J. Electron. Test. 5(2-3): 273-283 (1994) - 1991
- [c1]Vladimir Castro Alves, Michael Nicolaidis, P. Lestrat, Bernard Courtois:
Built-In Self-Test for Multi-Port RAMs. ICCAD 1991: 248-251
Coauthor Index
aka: Marcelo Soares Lubaszewski
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