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Frank M. L. van der Goes
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2010 – 2019
- 2018
- [j8]Rohan Sehgal
, Frank M. L. van der Goes, Klaas Bult
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. IEEE J. Solid State Circuits 53(7): 1878-1888 (2018) - [j7]Md Shakil Akter
A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. IEEE J. Solid State Circuits 53(10): 2939-2950 (2018) - 2017
- [c8]Rohan Sehgal
A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. ESSCIRC 2017: 131-134 - 2015
- [j6]Rohan Sehgal
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. IEEE J. Solid State Circuits 50(7): 1592-1603 (2015) - [c7]Md Shakil Akter, Rohan Sehgal
A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. ESSCIRC 2015: 315-318 - 2014
- [j5]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult:
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 2835-2845 (2014) - [c6]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC 2014: 1-8 - [c5]Rohan Sehgal
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. ESSCIRC 2014: 67-70 - [c4]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC 2014: 146-147 - [c3]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult:
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. ISSCC 2014: 200-201 - 2013
- [j4]Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult:
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. IEEE J. Solid State Circuits 48(7): 1595-1604 (2013) - 2011
- [j3]Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits 46(12): 2834-2844 (2011) - [c2]Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC 2011: 184-186
2000 – 2009
- 2009
- [j2]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3285-3293 (2009) - [c1]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. ISSCC 2009: 74-75 - 2004
- [j1]Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes:
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. IEEE J. Solid State Circuits 39(12): 2116-2125 (2004)
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