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Jeong-A Lee
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- affiliation: Chosun University, Department of Computer Engineering, Gwangju, South Korea
- affiliation: University of Houston, Department of Electrical Engineering, TX, USA
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2020 – today
- 2025
- [c46]Mohammadreza Najafi, Mohammad K. Fallah, Saeid Gorgin, Ghassem Jaberipur, Jeong-A Lee:
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture. WoWMoM 2025: 301-303 - 2024
- [j41]Mohammad K. Fallah, Mohammadreza Najafi, Saeid Gorgin
, Jeong-A Lee:
Abstraction and decision fusion architecture for resource-aware image understanding with application on handwriting character classification. Appl. Soft Comput. 162: 111813 (2024) - [j40]Mohammad K. Fallah
An ultra-low-computation model for understanding sign languages. Expert Syst. Appl. 249: 123782 (2024) - [c45]Zabihollah Ahmadpour, Ghassem Jaberipur, Jeong-A Lee:
Montgomery Modular Multiplication via Single-Base Residue Number Systems. ARITH 2024: 17-23 - [i8]Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee:
Modulo-(22n+1) Arithmetic via Two Parallel n-bit Residue Channels. CoRR abs/2404.08228 (2024) - [i7]Mohammad Sina Karvandi, Soroush Meghdadi Zanjani, Sima Arasteh, Saleh Khalaj Monfared, Mohammad K. Fallah, Saeid Gorgin, Jeong-A Lee, Erik van der Kouwe:
The Reversing Machine: Reconstructing Memory Assumptions. CoRR abs/2405.00298 (2024) - [i6]Malik Zohaib Nisar, Muhammad Sohail Ibrahim, Muhammad Usman, Jeong-A Lee:
L2R-CIPU: Efficient CNN Computation with Left-to-Right Composite Inner Product Units. CoRR abs/2406.00360 (2024) - [i5]Soudabeh Mousavi, Dara Rahmati, Saeid Gorgin, Jeong-A Lee:
Enhancing Computational Efficiency in Intensive Domains via Redundant Residue Number Systems. CoRR abs/2408.05639 (2024) - 2023
- [j39]Iraj Moghaddasi
Dependable DNN Accelerator for Safety-Critical Systems: A Review on the Aging Perspective. IEEE Access 11: 89803-89834 (2023) - [j38]Danial Javaheri
A new energy-efficient and temperature-aware routing protocol based on fuzzy logic for multi-WBANs. Ad Hoc Networks 139: 103042 (2023) - [j37]Danial Javaheri
Fuzzy logic-based DDoS attacks and network traffic anomaly detection methods: Classification, overview, and future perspectives. Inf. Sci. 626: 315-338 (2023) - [j36]Ghassem Jaberipur
A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3104-3108 (2023) - [j35]Umar Afzaal
On the Evolutionary Synthesis of Fault-Resilient Digital Circuits. IEEE Trans. Evol. Comput. 27(2): 281-295 (2023) - [j34]Mina Mirhosseini, Mahmood Fazlali
A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm. J. Supercomput. 79(11): 12042-12073 (2023) - [j33]Muhammad Usman
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. J. Signal Process. Syst. 95(7): 777-796 (2023) - [j32]Tooba Arifeen
Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product. J. Signal Process. Syst. 95(7): 815-829 (2023) - [c44]Saeid Gorgin, Mohammad H. Golamrezaei, Jeong-A Lee, Milos D. Ercegovac:
An Efficient Dot-Product Unit Based on Online Arithmetic for Variable Precision Applications. ACSSC 2023: 950-954 - [c43]Saeid Gorgin, Mohammadreza Najafi, Mohammad H. Golamrezaei, Jeong-A Lee, Milos D. Ercegovac:
MSDF-SVM: Advantage of Most Significant Digit First Arithmetic for SVM Realization. ACSSC 2023: 955-959 - [c42]Ghassem Jaberipur, Saeid Gorgin, Navid Ahamadian, Jeong-A Lee:
Modulo-(2q - 3) Multiplication with Fully Modular Partial Product Generation and Reduction. ARITH 2023: 68-75 - [c41]Muhammad Sohail Ibrahim
DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator. DSD 2023: 686-692 - [c40]Muhammad Akmal Shafique
CSA Based Radix-4 Gemmini Systolic Array for Machine Learning Applications. HEART 2023: 93-99 - [i4]Muhammad Usman, Milos D. Ercegovac, Jeong-A Lee:
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. CoRR abs/2304.12946 (2023) - [i3]Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar, Jeong-A Lee:
DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator. CoRR abs/2309.06019 (2023) - 2022
- [j31]Saeid Gorgin
A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier. IEEE Access 10: 11372-11381 (2022) - [j30]Danial Javaheri
An improved discrete harris hawk optimization algorithm for efficient workflow scheduling in multi-fog computing. Sustain. Comput. Informatics Syst. 36: 100787 (2022) - [c39]Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri
An Efficient FPGA Implementation of k-Nearest Neighbors via Online Arithmetic. FCCM 2022: 1-2 - [c38]Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri
An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First Arithmetic. FPT 2022: 1-4 - [c37]Najafi Mohammadreza
Ice Detection on Edge Device Based on Most Significant Digit First SVM. ICVIP 2022: 61-66 - [c36]Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri
kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation. SOCC 2022: 1-6 - [i2]Muhammad Usman, Jeong-A Lee, Milos D. Ercegovac:
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. CoRR abs/2204.09515 (2022) - 2021
- [c35]Muhammad Usman
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays. ACSCC 2021: 1-5 - [c34]Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee, Milos D. Ercegovac:
Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products. ACSCC 2021: 938-942 - 2020
- [j29]Tooba Arifeen, Abdus Sami Hassan
Approximate Triple Modular Redundancy: A Survey. IEEE Access 8: 139851-139867 (2020) - [j28]Umar Afzaal, Abdus Sami Hassan, Jeong-A Lee:
Improved error detection performance of logic implication checking in FPGA circuits. Microprocess. Microsystems 78: 103179 (2020) - [j27]Olufemi Adeluyi, Miguel A. Risco-Castillo
A Computerized Bioinspired Methodology for Lightweight and Reliable Neural Telemetry. Sensors 20(22): 6461 (2020) - [c33]Abdus Sami Hassan, Tooba Arifeen, Jeong-A Lee:
Data Footprint Reduction in DNN Inference by Sensitivity-Controlled Approximations with Online Arithmetic. DSD 2020: 534-541 - [c32]Umar Afzaal, Jeong-A Lee:
Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation. DSD 2020: 660-663 - [c31]Umar Afzaal, Jeong-A Lee:
Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems. ICTC 2020: 60-62 - [c30]Muhammad Usman
AMC-IoT: Automatic Modulation Classification Using Efficient Convolutional Neural Networks for Low Powered IoT Devices. ICTC 2020: 288-293
2010 – 2019
- 2019
- [j26]Sani Abba
Design and Performance Evaluation of a Low-Cost Autonomous Sensor Interface for a Smart IoT-Based Irrigation Monitoring and Control System. Sensors 19(17): 3643 (2019) - [j25]Inayat Ullah
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1298-1307 (2019) - [c29]Muhammad Usman
AFP-CKSAAP: Prediction of Antifreeze Proteins Using Composition of k-Spaced Amino Acid Pairs with Deep Neural Network. BIBE 2019: 38-43 - [i1]Muhammad Usman, Jeong-A Lee:
AFP-CKSAAP: Prediction of Antifreeze Proteins Using Composition of k-Spaced Amino Acid Pairs with Deep Neural Network. CoRR abs/1910.06392 (2019) - 2018
- [j24]Inayat Ullah
Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA. IEEE Access 6: 19940-19947 (2018) - [j23]Abdus Sami Hassan, Tooba Arifeen
Generation Methodology for Good-Enough Approximate Modules of ATMR. J. Electron. Test. 34(6): 651-665 (2018) - [j22]Zahid Ali Siddiqui
SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing. Sci. Program. 2018: 7306837:1-7306837:16 (2018) - [c28]Inayat Ullah, Umar Afzaal, Zahid Ullah, Jeong-A Lee:
High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA. DSD 2018: 16-21 - [c27]Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee:
Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL. DSD 2018: 190-195 - [c26]Umar Afzaal, Abdus Sami Hassan, Tooba Arifeen, Jeong-A Lee:
Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking. DSD 2018: 196-200 - 2017
- [j21]Sani Abba, Jeong-A Lee:
Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization. Microprocess. Microsystems 51: 18-38 (2017) - [j20]Hossein Moradian, Jeong-A Lee, Joonsang Yu:
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept. J. Signal Process. Syst. 88(3): 297-309 (2017) - [c25]Umar Afzaal, Jeong-A Lee:
FPGA-based design of a self-checking TMR voter. FPL 2017: 1-4 - 2016
- [j19]Sani Abba, Jeong-A Lee:
FPGA-Based Design of an Intelligent On-Chip Sensor Network Monitoring and Control Using Dynamically Reconfigurable Autonomous Sensor Agents. Int. J. Distributed Sens. Networks 12(2): 4246596:1-4246596:29 (2016) - [j18]Hossein Moradian, Jeong-A Lee, Adnan Hashmi:
Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization. Microelectron. Reliab. 63: 256-266 (2016) - [c24]Tooba Arifeen, Abdus Sami Hassan, Hossein Moradian, Jeong-A Lee:
Probing Approximate TMR in Error Resilient Applications for Better Design Tradeoffs. DSD 2016: 637-640 - 2015
- [j17]Masoud Afrakhteh, Inkyu Moon, Jeong-A Lee:
Double phase modular steganography with the help of error images. Multim. Tools Appl. 74(13): 4833-4847 (2015) - [j16]Masoud Afrakhteh, Jeong-A Lee:
Adaptive least significant bit matching revisited with the help of error images. Secur. Commun. Networks 8(3): 510-515 (2015) - [j15]Masoud Afrakhteh, Jeong-A Lee:
Parallel modular steganography using error images. Secur. Commun. Networks 8(8): 1515-1524 (2015) - [j14]Sani Abba
An Autonomous Self-Aware and Adaptive Fault Tolerant Routing Technique for Wireless Sensor Networks. Sensors 15(8): 20316-20354 (2015) - [c23]Hossein Moradian, Jeong-A Lee:
Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept. DSD 2015: 276-279 - 2014
- [j13]Sani Abba, Jeong-A Lee:
A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip. Microprocess. Microsystems 38(5): 375-398 (2014) - [j12]Muhammad Ali Akbar, Jeong-A Lee:
Self-repairing adder using fault localization. Microelectron. Reliab. 54(6-7): 1443-1451 (2014) - [j11]Muhammad Ali Akbar, Jeong-A Lee:
Comments on "Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding". IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2212-2214 (2014) - 2013
- [c22]Muhammad Ali Akbar, Jeong-A Lee:
Self-Checking Carry Select Adder with Fault Localization. DSD 2013: 863-869 - [c21]Zahid Ali Siddiqui, Park Hui-Jong, Jeong-A Lee:
Area-Time Efficient Self-Checking ALU Based on Scalable Error Detection Coding. DSD 2013: 870-877 - [c20]Hasan Baig, Jeong-A Lee:
A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only). FPGA 2013: 270 - 2012
- [c19]Hasan Baig
An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities. FPT 2012: 301-304 - [c18]Olufemi Adeluyi, Jeong-A Lee:
SMiRA: A bio-inspired fault tolerant routing algorithm for MANETs. ICTC 2012: 78-84 - [c17]Olufemi Adeluyi, Sidra Riaz, Sangman Moh, Sang-Woong Lee, Jeong-A Lee:
SAFE-points: a lightweight algorithm for analyzing remote mobile ECG signals. mHealthSys@SenSys 2012: 8:1-8:2 - 2010
- [j10]Olufemi Adeluyi, Jeong-A Lee:
Reconfiguration for Sensitivity Technique: A QoS-aware Co-Design approach for stream-based applications. IEICE Electron. Express 7(24): 1766-1772 (2010) - [c16]Young Jin Park, Min Zeng, Byeong-Seok Lee, Jeong-A Lee, Seung Gu Kang, Cheol Hong Kim:
Thermal Analysis for 3D Multi-core Processors with Dynamic Frequency Scaling. ACIS-ICIS 2010: 69-74
2000 – 2009
- 2009
- [j9]Min Zeng, Jeong-Gun Lee, Goang-Seog Choi, Jeong-A Lee:
Intelligent sensor node based a low power ECG monitoring system. IEICE Electron. Express 6(9): 560-565 (2009) - [j8]Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee:
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. J. Circuits Syst. Comput. 18(4): 787-800 (2009) - 2007
- [j7]Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. J. VLSI Signal Process. 46(2-3): 133-151 (2007) - [c15]Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac:
A Design Method for Heterogeneous Adders. ICESS 2007: 121-132 - [e2]Sio Iong Ao, Oscar Castillo, Craig Douglas, David Dagan Feng, Jeong-A Lee:
Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, March 21-23, 2007, Hong Kong, China. Lecture Notes in Engineering and Computer Science, Newswood Limited 2007, ISBN 978-988-98671-4-0 [contents] - 2006
- [e1]Sio Iong Ao, Jeong-A Lee, Oscar Castillo, Pranay Chaudhuri, David Dagan Feng:
Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, IMECS '06, June 20-22, 2006, Hong Kong, China. Lecture Notes in Engineering and Computer Science, Newswood Limited 2006, ISBN 988-98671-3-3 [contents] - 2005
- [j6]Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, Kiseon Kim:
A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1031-1037 (2005) - [j5]Jeong-Gun Lee, Jeong-A Lee, Suk-Jin Kim, Kiseon Kim:
Design of a Mutated Adder and Its Optimization Using ILP Formulation. IEICE Trans. Inf. Syst. 88-D(7): 1506-1508 (2005) - [j4]Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Son Jhang
Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion. IEICE Trans. Electron. 88-C(12): 2395-2399 (2005) - [c14]Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har:
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. ACM Great Lakes Symposium on VLSI 2005: 152-155 - [c13]Eun-Gu Jung, Eonpyo Hong, Kyoung-Son Jhang
Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs. PCM (1) 2005: 500-511 - 2004
- [c12]Seong-Yong Ahn, Jun-Yong Kim, Jeong-A Lee:
Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System. Asia-Pacific Computer Systems Architecture Conference 2004: 102-114 - [c11]Byung-Soo Choi, Jeong-A Lee, Dong-Soo Har:
High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption. Asia-Pacific Computer Systems Architecture Conference 2004: 170-184 - [c10]Jeong-Gun Lee, Euiseok Kim, Jeong-A Lee, Eunok Paek:
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization. Asia-Pacific Computer Systems Architecture Conference 2004: 582-595 - [c9]Dong-Hoon Yoo, Dong-Ik Lee, Jeong-A Lee:
Operation Net System: A Formal Design Representation Model for High-Level Synthesis of Asynchronous Systems Based on Transformations. ICATPN 2004: 435-453 - [c8]Seung Soo Lee, Jeong-A Lee, Chang Choon Park:
A research of merging regions through isophotes analysis. ISICT 2004: 208-213 - 2003
- [c7]Seong-Yong Ahn, Yo-Seop Hwang, Jae-Hong Shim, Jeong-A Lee:
Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC. Engineering of Reconfigurable Systems and Algorithms 2003: 325- - [c6]Sangman Moh, Jae-Hong Shim, Yang-Dong Lee, Jeong-A Lee, Beom-Joon Cho:
Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net. ISCIS 2003: 908-915 - 2000
- [j3]Gerben J. Hekstra, Ed F. Deprettere, Jeong-A Lee:
Guest Editor's Introduction. J. VLSI Signal Process. 25(2): 99-100 (2000) - [j2]Kees-Jan van der Kolk, Jeong-A Lee, Ed F. Deprettere:
A Floating Point Vectoring Algorithm Based on Fast Rotations. J. VLSI Signal Process. 25(2): 125-139 (2000)
1990 – 1999
- 1999
- [c5]Kees-Jan van der Kolk, Ed F. Deprettere, Jeong-A Lee:
A Floating Point Vectoring Algorithm Based on Fast Rotations. EUROMICRO 1999: 1140- - 1994
- [c4]Jeong-A Lee, Mubashir Ahmad:
VLSI implementation of CORDIC angle units. Great Lakes Symposium on VLSI 1994: 144-149 - 1992
- [j1]Jeong-A Lee, Tomás Lang:
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation. IEEE Trans. Computers 41(8): 1016-1025 (1992) - 1991
- [c3]Jeong-A Lee, Tomás Lang:
SVD by constant-factor-redundant-CORDIC. IEEE Symposium on Computer Arithmetic 1991: 264-271 - [c2]Jeong-A Lee, Kiseon Kim:
Discrete Fourier transform processors using CORDIC. Great Lakes Symposium on VLSI 1991: 260-265 - [c1]John A. Harding, Tomás Lang, Jeong-A Lee:
A Comparison of Redundant CORDIC Rotation Engines. ICCD 1991: 556-559
Coauthor Index
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