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Roshan Weerasekera
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2020 – today
- 2024
- [j6]Disala Uduwawala
, Roshan Weerasekera
Incident and Load Power Relations in a Mismatched Lossless Transmission Line. Circuits Syst. Signal Process. 43(9): 6011-6022 (2024) - 2023
- [j5]Richard Mayne
Propagation of electrical signals by fungi. Biosyst. 229: 104933 (2023) - [p1]Neil Phillips, Roshan Weerasekera, Nic Roberts, Andrew Adamatzky:
Electrical Signal Transfer by Fungi. Fungal Machines 2023: 227-242 - [i3]Richard Mayne, Nic Roberts, Neil Phillips, Roshan Weerasekera
Propagation of electrical signals by fungi. CoRR abs/2304.10675 (2023)
2010 – 2019
- 2019
- [i2]Richard Mayne, Thomas C. Draper, Neil Phillips, James Gerald Holland Whiting, Roshan Weerasekera
Neuromorphic Liquid Marbles With Aqueous Carbon Nanotube Cores. CoRR abs/1906.08099 (2019) - 2018
- [i1]Andrew Adamatzky, Neil Phillips, Roshan Weerasekera
Excitable London: Street map analysis with Oregonator model. CoRR abs/1803.01632 (2018) - 2015
- [j4]Guruprasad Katti, S. W. Ho, Li Hong Yu, Songbai Zhang, Rahul Dutta, Roshan Weerasekera
Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI). IEEE Des. Test 32(4): 23-31 (2015) - [j3]Chao Wang, Jun Zhou, Roshan Weerasekera
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 139-148 (2015) - 2013
- [c17]Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 3DIC 2013: 1-4 - 2011
- [c16]Joseph Romen Cubillo, Roshan Weerasekera
Interconnect design and analysis for Through Silicon Interposers (TSIs). 3DIC 2011: 1-6 - [c15]Yuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu, Roshan Weerasekera
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. 3DIC 2011: 1-6 - [c14]Matthew Grange, Axel Jantsch
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317 - [c13]Matt Grange, Roshan Weerasekera
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64 - [c12]Dinesh Pamunuwa
3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348 - 2010
- [c11]Roshan Weerasekera
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
2000 – 2009
- 2009
- [j2]Roshan Weerasekera
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1237-1250 (2009) - [c10]Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 - [c9]Roshan Weerasekera
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8 - [c8]Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera
3-D memory organization and performance analysis for multi-processor network-on-chip architecture. 3DIC 2009: 1-7 - [c7]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123 - 2008
- [b1]Roshan Weerasekera:
System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits. KTH Royal Institute of Technology, Sweden, 2008 - [j1]Roshan Weerasekera
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 589-593 (2008) - 2007
- [c6]Roshan Weerasekera
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219 - [c5]Roshan Weerasekera
Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC 2007: 187-190 - [c4]Roshan Weerasekera
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313 - 2006
- [c3]Roshan Weerasekera
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120 - 2005
- [c2]Roshan Weerasekera
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285 - 2004
- [c1]Roshan Weerasekera
Crosstalk immune interconnect driver design. SoC 2004: 139-142
Coauthor Index
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