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Brian T. Murray
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2000 – 2009
- 2005
- [j13]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Dependable communication synthesis for distributed embedded systems. Reliab. Eng. Syst. Saf. 89(1): 81-92 (2005) - [j12]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. IEEE Trans. Parallel Distributed Syst. 16(3): 258-270 (2005) - 2003
- [c11]Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray:
Low-Cost On-Line Fault Detection Using Control Flow Assertions. IOLTS 2003: 137-143 - [c10]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Dependable Communication Synthesis for Distributed Embedded Systems. SAFECOMP 2003: 275-288 - 2002
- [c9]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems. DSN 2002: 449-458 - 2000
- [j11]Krishnendu Chakrabarty
, Brian T. Murray, Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 633-636 (2000) - [c8]Barbara J. Czerny, Joseph G. D'Ambrosio, Brian T. Murray:
Providing convincing evidence of safety in X-by-wire automotive systems. HASE 2000: 189-192
1990 – 1999
- 1999
- [j10]Vikram Iyengar, Krishnendu Chakrabarty
Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electron. Test. 15(1-2): 97-114 (1999) - [c7]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. SRDS 1999: 212-221 - [c6]Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27 - 1998
- [j9]Hussain Al-Asaad, Brian T. Murray, John P. Hayes:
Online BIST for Embedded Systems. IEEE Des. Test Comput. 15(4): 17-24 (1998) - [j8]Hussain Al-Asaad, John P. Hayes, Brian T. Murray:
Scalable Test Generators for High-Speed Datapath Circuits. J. Electron. Test. 12(1-2): 111-125 (1998) - [j7]Krishnendu Chakrabarty
Optimal Zero-Aliasing Space Compaction of Test Responses. IEEE Trans. Computers 47(11): 1171-1187 (1998) - [j6]Krishnendu Chakrabarty
Design of built-in test generator circuits using width compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1044-1051 (1998) - [j5]Vikram Iyengar, Krishnendu Chakrabarty
Huffman encoding of test sets for sequential circuits. IEEE Trans. Instrum. Meas. 47(1): 21-25 (1998) - [c5]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423 - 1997
- [c4]Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray:
Test Width Compression for Built-In Self Testing. ITC 1997: 328-337 - 1996
- [j4]Brian T. Murray, John P. Hayes:
Testing ICs: Getting to the Core of the Problem. Computer 29(11): 32-38 (1996) - 1995
- [c3]Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes:
Optimal Space Compaction of Test Responses. ITC 1995: 834-843 - 1994
- [b1]Brian T. Murray:
Hierarchical testing using precomputed tests for modules. University of Michigan, USA, 1994 - [j3]Xiaobo Hu
Codesign of architectures for automotive powertrain modules. IEEE Micro 14(4): 17-25 (1994) - 1991
- [c2]Brian T. Murray, John P. Hayes:
Test Propagation Through Modules and Circuits. ITC 1991: 748-757 - 1990
- [j2]Brian T. Murray, John P. Hayes:
Hierarchical test generation using precomputed tests for modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 594-603 (1990)
1980 – 1989
- 1989
- [j1]Debashis Bhattacharya, Brian T. Murray, John P. Hayes:
High-Level Test Generation for VLSI. Computer 22(4): 16-24 (1989) - 1988
- [c1]Brian T. Murray, John P. Hayes:
Hierarchical Test Generation Using Precomputed Tests for Modules. ITC 1988: 221-229
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