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Steven G. Rothweiler
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1990 – 1999
- 1997
- [j2]Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal:
Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1370-1377 (1997) - [c7]Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler:
Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design 1997: 488-494 - 1995
- [c6]Srimat T. Chakradhar, Steven G. Rothweiler:
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. VTS 1995: 12-19 - 1993
- [j1]Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler:
A transitive closure algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1015-1028 (1993) - [c5]Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
Sequential Circuit Delay optimization Using Global Path Delays. DAC 1993: 483-489 - 1992
- [c4]Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
Performance optimization of sequential circuits by eliminating retiming bottlenecks. ICCAD 1992: 504-509
1980 – 1989
- 1989
- [c3]Chia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu:
Mind: a module binder for high level synthesis. ICCD 1989: 420-423 - 1988
- [c2]Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou:
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC 1988: 409-414 - [c1]Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose:
Bridge: A Versatile Behavioral Synthesis System. DAC 1988: 415-420
Coauthor Index
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