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Gi-Ho Park
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2020 – today
- 2024
- [c16]Guhyun Kim, Jinkwon Kim, Nahsung Kim, Woojae Shin, Jongsoon Won, Hyunha Joo, Haerang Choi, Byeongju An, Gyeongcheol Shin, Dayeon Yun, Jeongbin Kim, Changhyun Kim, Ilkon Kim, Jaehan Park, Yosub Song, Byeongsu Yang, Hyeongdeok Lee, Seungyeong Park, Wonjun Lee, Seonghun Kim, Yonghoon Park, Yousub Jung, Gi-Ho Park, Euicheol Lim:
SK Hynix AI-Specific Computing Memory Solution: From AiM Device to Heterogeneous AiMX-xPU System for Comprehensive LLM Inference. HCS 2024: 1-26 - 2023
- [j31]Min-Kwan Kee
, Chiwon Han, Gi-Ho Park
An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator. IEEE Access 11: 78726-78736 (2023) - [j30]Jaeung Lee, Chiwon Han, Kyungeun Kim, Gi-Ho Park
CaMeL-Net: Centroid-aware metric learning for efficient multi-class cancer classification in pathology images. Comput. Methods Programs Biomed. 241: 107749 (2023) - 2022
- [j29]Min-Kwan Kee
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices. ACM Trans. Design Autom. Electr. Syst. 27(5): 51:1-51:13 (2022)
2010 – 2019
- 2018
- [j28]Duk-Jun Bang, Min-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park:
An adaptive cache replacement policy based on fine-grain reusability monitor. IEICE Electron. Express 15(2): 20171099 (2018) - 2017
- [j27]Seung-Jin Lee, Min-Kwan Kee, Gi-Ho Park:
Sensor data compression and power management scheme for low power sensor hub. IEICE Electron. Express 14(23): 20170974 (2017) - [j26]Min-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park, Sangyeun Cho:
An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems. J. Parallel Distributed Comput. 100: 172-180 (2017) - [j25]Ju Hee Choi
NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors. IEEE Trans. Parallel Distributed Syst. 28(10): 2896-2910 (2017) - [c15]Min-Kwan Kee, Seung-Jin Lee, Hyun-Su Seon, Jongsung Lee, Gi-Ho Park:
Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC. COOL Chips 2017: 1-3 - 2016
- [j24]Ju Hee Choi
Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture. Comput. J. 59(5): 685-700 (2016) - [j23]Hong-Yeol Lim, Gi-Ho Park:
Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system. IEICE Electron. Express 13(12): 20160276 (2016) - 2015
- [j22]Sung-In Jang, Su-Kyung Yoon, Kihyun Park, Gi-Ho Park, Shin-Dug Kim:
Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory. Comput. J. 58(11): 2852-2863 (2015) - [j21]Hyojong Kim, Hong-Yeol Lim, Dilan Manatunga, Hyesoon Kim, Gi-Ho Park:
Accelerating Application Start-up with Nonvolatile Memory in Android Systems. IEEE Micro 35(1): 15-25 (2015) - 2014
- [j20]Ju Hee Choi
Adaptive replacement policy for hybrid cache architecture. IEICE Electron. Express 11(22): 20140946 (2014) - 2013
- [j19]Hong-Yeol Lim, Gi-Ho Park:
Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology. IEICE Electron. Express 10(4): 20120971 (2013) - [j18]Hong-Yeol Lim, Gi-Ho Park:
An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology. IEICE Electron. Express 10(16): 20130523 (2013) - [c14]Hong-Yeol Lim, Min-Kwan Kee, Gi-Ho Park:
Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits. 3DIC 2013: 1-5 - 2012
- [c13]Byung-Min Lee, Gi-Ho Park:
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM. ISOCC 2012: 247-250 - 2011
- [c12]Hong-Yeol Lim, Gi-Ho Park:
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology. 3DIC 2011: 1-5 - 2010
- [j17]Gunok Jung, Gi-Ho Park, Ukrae Cho, Jae-Cheol Son:
Fully digital clock frequency doubler. IEICE Electron. Express 7(6): 416-420 (2010) - [j16]Jung-Wook Park
An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing. J. Parallel Distributed Comput. 70(11): 1110-1118 (2010) - [j15]Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC). Microprocess. Microsystems 34(2-4): 102-116 (2010)
2000 – 2009
- 2009
- [j14]Jung-Wook Park
Sub-grouped superblock management for high-performance flash storages. IEICE Electron. Express 6(6): 297-303 (2009) - [j13]Jung-Wook Park
An integrated mapping table for hybrid FTL with fault-tolerant address cache. IEICE Electron. Express 6(7): 368-374 (2009) - [j12]Gi-Ho Park, Jung-Wook Park
A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache. IEICE Trans. Electron. 92-C(4): 517-521 (2009) - [j11]Gi-Ho Park, Jung-Wook Park
Low-Power Embedded Processor Design Using Branch Direction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3180-3181 (2009) - 2008
- [j10]Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park:
Power and Skew Aware Point Diffusion Clock Network. IEICE Trans. Electron. 91-C(11): 1832-1834 (2008) - 2007
- [j9]Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim:
Cooperative Cache System: A Low Power Cache System for Embedded Processors. IEICE Trans. Electron. 90-C(4): 708-717 (2007) - [c11]Jung-Min Park, Jung-Wook Park, Cheong-Ghil Kim, Gi-Ho Park, Shin-Dug Kim:
An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC. PDCS 2007: 169-174 - [c10]Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park:
Performance monitor unit design for an AXI-based multi-core SoC platform. SAC 2007: 1565-1572 - 2006
- [j8]Sung Woo Chung, Gi-Ho Park, Hyo-Joong Suh, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park
Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator. Microprocess. Microsystems 30(3): 137-144 (2006) - [j7]Jung-Wook Park
A deterministic way-prediction scheme using power-aware replacement policy. Microprocess. Microsystems 30(4): 209-215 (2006) - [c9]Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim:
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 574-580 - [c8]Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park
Practice and Experience of an Embedded Processor Core Modeling. HPCC 2006: 621-630 - 2005
- [b1]Gi-Ho Park:
p-Refinement Techniques for Vector Finite Elements in Electromagnetics. Georgia Institute of Technology, Atlanta, GA, USA, 2005 - [j6]Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities. J. Syst. Archit. 51(2): 111-123 (2005) - 2004
- [j5]Sung Woo Chung, Gi-Ho Park, Sung-Bae Park:
A Low-Power Tournament Branch Predictor. IEICE Trans. Inf. Syst. 87-D(7): 1962-1964 (2004) - [j4]Sung Woo Chung, Gi-Ho Park, Sung-Bae Park:
A Low-Power Branch Predictor for Embedded Processors. IEICE Trans. Inf. Syst. 87-D(9): 2253-2257 (2004) - [j3]Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
Dynamic and selective low power data TLB system. Microprocess. Microsystems 28(3): 95-105 (2004) - [c7]Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim:
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. ICCD 2004: 42-47 - 2003
- [c6]Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
Appliaction-Specific Data Cache Systems. CATA 2003: 408-412 - [c5]Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim:
A selective filter-bank TLB system. ISLPED 2003: 312-317 - [c4]Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications. PDP 2003: 109- - 2002
- [c3]Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim:
An Advanced Filtering TLB for Low Power Consumption. SBAC-PAD 2002: 93-99 - 2000
- [c2]Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim:
A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure. LCTES 2000: 162-177 - [c1]Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim:
A Dual Data Cache System to Reflect the Principle of Locality Effectively. PDPTA 2000
1990 – 1999
- 1998
- [j2]Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang:
Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors. J. Syst. Archit. 44(9-10): 755-772 (1998) - 1996
- [j1]Oh-Young Kwon, Gi-Ho Park, Tack-Don Han:
A compiler optimization to reduce execution time of loop nest. SIGARCH Comput. Archit. News 24(1): 6-11 (1996)
Coauthor Index
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