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Scott Lerner
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2020 – today
- 2024
- [c13]Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin:
Design Automation for Charge Recovery Logic. ISCAS 2024: 1-5 - 2021
- [j3]Ragh Kuttappa
, Baris Taskin
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1636-1645 (2021)
2010 – 2019
- 2019
- [j2]Scott Lerner
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 1-10 (2019) - [j1]Scott Lerner
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 700-710 (2019) - [c12]Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin:
Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS 2019: 1-5 - [c11]Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis:
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED 2019: 1-6 - 2018
- [c10]Scott Lerner, Baris Taskin:
Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. IGSC 2018: 1-6 - [c9]Scott Lerner, Vasil Pano, Baris Taskin:
NoC Router Lifetime Improvement using Per-Port Router Utilization. ISCAS 2018: 1-5 - [c8]Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin:
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. ISCAS 2018: 1-5 - 2017
- [c7]Ragh Kuttappa, Leo Filippini
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS 2017: 1-4 - [c6]Scott Lerner, Baris Taskin:
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. ISQED 2017: 379-384 - [c5]Scott Lerner, Baris Taskin:
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. ISVLSI 2017: 465-470 - [c4]Scott Lerner, Eric Leggett, Baris Taskin:
Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP 2017: 1-4 - 2015
- [c3]Siddharth Nilakantan
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. VLSID 2015: 135-140 - 2014
- [c2]Can Sitik, Scott Lerner, Baris Taskin:
Timing characterization of clock buffers for clock tree synthesis. ICCD 2014: 230-236
2000 – 2009
- 2008
- [c1]Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang
A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Hot Interconnects 2008: 3-10
Coauthor Index
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