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Thomas W. Fox
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2020 – today
- 2020
- [j4]Swagath Venkataramani
, Xiao Sun
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [c5]Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c4]Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED 2018: 35:1-35:2 - [c3]Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits 2018: 35-36 - 2015
- [j3]Ravi Nair, Samuel Antão, Carlo Bertolli, Pradip Bose, José R. Brunheroto, Tong Chen, Chen-Yong Cher, Carlos H. A. Costa, J. Doi, Constantinos Evangelinos, Bruce M. Fleischer, Thomas W. Fox, Diego S. Gallo, Leopold Grinberg, John A. Gunnels, Arpith C. Jacob, P. Jacob, Hans M. Jacobson, Tejas Karkhanis, C. Kim, Jaime H. Moreno, John K. O'Brien, Martin Ohmacht
Active Memory Cube: A processing-in-memory architecture for exascale systems. IBM J. Res. Dev. 59(2/3) (2015) - 2012
- [j2]Ruud A. Haring, Martin Ohmacht
The IBM Blue Gene/Q Compute Chip. IEEE Micro 32(2): 48-60 (2012) - 2011
- [c2]Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258
2000 – 2009
- 2004
- [c1]Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno:
Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452 - 2003
- [j1]Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter:
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47(2-3): 299-326 (2003)
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