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Jaejun Yoon
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2020 – today
- 2022
- [c1]Dae-Hyun Kim
, Byungkyu Song, Hyun-A. Ahn
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC 2022: 448-450
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last updated on 2024-04-24 22:47 CEST by the dblp team
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