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Ahmed E. AbdelRahman
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2020 – today
- 2024
- [c8]Mahmoud A. Khalil
, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang, Kyu-Sang Park
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. ISSCC 2024: 138-140 - 2023
- [j3]Yongxin Li
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. IEEE J. Solid State Circuits 58(3): 785-795 (2023) - [j2]Kyu-Sang Park
A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C. IEEE J. Solid State Circuits 58(7): 2064-2074 (2023) - [j1]Kyu-Sang Park
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C. IEEE J. Solid State Circuits 58(12): 3459-3469 (2023) - [c7]Kyu-Sang Park
A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$. ISSCC 2023: 62-63 - [c6]Ahmed E. AbdelRahman
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. ISSCC 2023: 208-209 - [c5]Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c4]Yongxin Li
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. CICC 2022: 1-2 - 2021
- [c3]Kyu-Sang Park
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C. CICC 2021: 1-2 - [c2]Muhamed F. Allam, Ahmed E. AbdelRahman
Novel Decimation Topology with Improved Jitter Performance for Clock and Data Recovery Systems. NEWCAS 2021: 1-4
2010 – 2019
- 2016
- [c1]Ahmed E. AbdelRahman
A fast-locking all-digital clock and data recovery circuit using successive approximation. MWSCAS 2016: 1-4
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