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Ssu-Wei Huang

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2020 – today

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2020
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  - journals/tcas/LeeHW20
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Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang:
A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. IEEE Trans. Circuits Syst. 67-II(11): 2707-2711 (2020)

2010 – 2019

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2018
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  - conf/apccas/WangHH18
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Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang:
40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. APCCAS 2018: 279-282

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