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Yoonseo Cho
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2020 – today
- 2024
- [i1]Jaesung Park, Sungchul Hong, Yoonseo Cho, Jong-June Jeon:
Unicorn: U-Net for Sea Ice Forecasting with Convolutional Neural Ordinary Differential Equations. CoRR abs/2405.03929 (2024) - 2023
- [c4]Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi:
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter. CICC 2023: 1-2 - [c3]Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi:
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j2]Suneui Park
, Seojin Choi
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. IEEE J. Solid State Circuits 57(9): 2829-2840 (2022) - 2021
- [c2]Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi:
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. ISSCC 2021: 330-332
2010 – 2019
- 2019
- [j1]Juyeop Kim
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE J. Solid State Circuits 54(12): 3466-3477 (2019) - [c1]Juyeop Kim
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. ISSCC 2019: 258-260
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