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Daniel Pollex
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2010 – 2019
- 2011
- [c5]Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. ISSCC 2011: 194-196 - 2010
- [c4]Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang:
A 40GS/s 6b ADC in 65nm CMOS. ISSCC 2010: 390-391
2000 – 2009
- 2009
- [c3]Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt:
Clock recovery for a 40 Gb/s QPSK optical receiver. ICECS 2009: 695-698 - 2008
- [c2]Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski:
A 24GS/s 6b ADC in 90nm CMOS. ISSCC 2008: 544-545 - 2006
- [c1]Peter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben-Hamida:
A 22GS/s 5b adc in 0.13µm SiGe BiCMOS. ISSCC 2006: 2340-2349
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last updated on 2024-04-24 22:52 CEST by the dblp team
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