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Basant K. Mohanty
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2020 – today
- 2024
- [j36]Basant Kumar Mohanty
:
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 695-703 (2024) - 2023
- [j35]Rehan Ahmad
A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage. Turkish J. Electr. Eng. Comput. Sci. 31(7): 1237-1254 (2023) - [j34]Basant Kumar Mohanty
Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 165-174 (2023) - 2021
- [j33]Rehan Ahmad
Chronic kidney disease stage identification using texture analysis of ultrasound images. Biomed. Signal Process. Control. 69: 102695 (2021) - 2020
- [j32]Subodh Kumar Singhal
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29(12): 2050186:1-2050186:20 (2020) - [j31]Basant Kumar Mohanty
Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform. IEEE Trans. Circuits Syst. Video Technol. 30(12): 4944-4952 (2020) - [j30]Basant Kumar Mohanty
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1221-1229 (2020)
2010 – 2019
- 2019
- [j29]Basant Kumar Mohanty
Efficient Fixed-Width Adder-Tree Design. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 292-296 (2019) - [j28]Basant K. Mohanty
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1042-1050 (2019) - 2018
- [j27]Vasundhara
Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids. Circuits Syst. Signal Process. 37(4): 1383-1406 (2018) - [j26]Abhishek Choubey
Novel Data-Access Scheme and Efficient Parallel Architecture for Multi-level Lifting 2-D DWT. Circuits Syst. Signal Process. 37(10): 4482-4503 (2018) - 2017
- [j25]Basant Kumar Mohanty
Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers. Circuits Syst. Signal Process. 36(2): 447-473 (2017) - [j24]Basant Kumar Mohanty
Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT. Circuits Syst. Signal Process. 36(3): 1129-1149 (2017) - 2016
- [j23]Basant Kumar Mohanty
Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer. Circuits Syst. Signal Process. 35(8): 2958-2971 (2016) - [j22]Basant Kumar Mohanty
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integr. 54: 37-46 (2016) - [j21]Subodh Kumar Singhal
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic. J. Circuits Syst. Comput. 25(7): 1650073:1-1650073:19 (2016) - [j20]Basant Kumar Mohanty
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 444-452 (2016) - [j19]Basant K. Mohanty
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1926-1935 (2016) - 2015
- [j18]Basant Kumar Mohanty
Efficient very large-scale integration architecture for variable length block least mean square adaptive filter. IET Signal Process. 9(8): 605-610 (2015) - [j17]Basant Kumar Mohanty
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 283-291 (2015) - [j16]Pramod Kumar Meher, Basant Kumar Mohanty
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2836-2845 (2015) - [j15]Hassan Rabah
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2209-2220 (2015) - [c13]Carlo Safarian, Tokunbo Ogunfunmi
FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications. DSP 2015: 1251-1255 - [c12]Vivek Chaturvedi
Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems. DSP 2015: 1266-1269 - [c11]Basant K. Mohanty
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems. DSP 2015: 1270-1273 - [c10]Basant K. Mohanty
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. ISCAS 2015: 1186-1189 - [c9]Pramod Kumar Meher, Basant Kumar Mohanty
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. VLSID 2015: 327-332 - 2014
- [j14]Basant K. Mohanty
Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier. Circuits Syst. Signal Process. 33(12): 3981-3994 (2014) - [j13]Basant K. Mohanty
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. IET Image Process. 8(6): 345-353 (2014) - [j12]Basant K. Mohanty
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 120-133 (2014) - [j11]Basant Kumar Mohanty
Area-Delay-Power Efficient Carry-Select Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 418-422 (2014) - [j10]Pramod Kumar Meher, Sang Yoon Park, Basant Kumar Mohanty
Efficient Integer DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 24(1): 168-178 (2014) - [c8]Pramod Kumar Meher, Basant K. Mohanty
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. ISCAS 2014: 2628-2631 - 2013
- [j9]Basant K. Mohanty
Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer. IET Circuits Devices Syst. 7(6): 319-325 (2013) - [j8]Basant K. Mohanty
Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT. J. Low Power Electron. 9(1): 37-44 (2013) - [j7]Basant K. Mohanty
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. 23(2): 353-363 (2013) - [j6]Basant K. Mohanty
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. IEEE Trans. Signal Process. 61(4): 921-932 (2013) - [c7]Basant K. Mohanty
Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank. IDT 2013: 1-6 - 2012
- [j5]Basant K. Mohanty
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 434-438 (2012) - [c6]Basant K. Mohanty
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS 2012: 1480-1483 - 2011
- [j4]Basant K. Mohanty
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. IEEE Trans. Signal Process. 59(5): 2072-2084 (2011) - [j3]Basant K. Mohanty
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. IEEE Trans. Signal Process. 59(11): 5605-5616 (2011) - 2010
- [j2]Basant K. Mohanty
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. IEEE Trans. Circuits Syst. Video Technol. 20(9): 1200-1209 (2010) - [c5]Anurag Mahajan
Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic. APCCAS 2010: 1195-1198
2000 – 2009
- 2008
- [j1]Pramod Kumar Meher, Basant K. Mohanty
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 151-155 (2008) - [c4]Basant K. Mohanty
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. ASAP 2008: 162-166 - [c3]Basant K. Mohanty
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. ASAP 2008: 305-309 - 2006
- [c2]Basant K. Mohanty
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. APCCAS 2006: 458-461 - [c1]Basant K. Mohanty
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. APCCAS 2006: 462-465
Coauthor Index
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