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Viveka Konandur Rajanna
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2020 – today
- 2024
- [c12]Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto:
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c11]Karim Ali Ahmed, Ruiyuan Yang, Praveenakumar Shivappa Salamani, Viveka Konandur Rajanna, Massimo Alioto:
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems. ESSCIRC 2023: 49-52 - [c10]Viveka Konandur Rajanna:
Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads. iSES 2023: 210-211 - [c9]Joydeep Basu
, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto:
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. VLSI Technology and Circuits 2023: 1-2 - [c8]Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j3]Sachin Taneja
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. IEEE J. Solid State Circuits 57(1): 153-166 (2022) - [c7]Animesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto:
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm. CICC 2022: 1-2 - [c6]Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks. VLSI Technology and Circuits 2022: 144-145 - 2021
- [j2]Viveka Konandur Rajanna
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications. IEEE J. Solid State Circuits 56(11): 3533-3543 (2021) - [c5]Viveka Konandur Rajanna
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSCIRC 2021: 127-130 - [c4]Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSDERC 2021: 127-130 - [c3]Sachin Taneja, Viveka Konandur Rajanna
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. ISSCC 2021: 498-500 - [c2]Prachi Agarwal
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c1]Viveka Konandur Rajanna
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications. CICC 2019: 1-4 - 2016
- [j1]Viveka Konandur Rajanna
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1663-1674 (2016)
Coauthor Index
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