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Sungpill Choi
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2020 – today
- 2024
- [c19]Chang-Hyo Yu, Hyo-Eun Kim, Sungho Shin, Kyeongryeol Bong, Hyunsuk Kim, Yoonho Boo, Jaewan Bae, Minjae Kwon, Karim Charfi, Jinseok Kim, Hongyun Kim, Myeongbo Shim, Changsoo Ha, Wongyu Shin, Jae-Sung Yoon, Miock Chi, Byungjae Lee, Sungpill Choi, Donghan Kim, Jeongseok Woo, Seokju Yoon, Hyunje Jo, Hyunho Kim, Hyun-Seok Heo, Young-Jae Jin, Jiun Yu, Jaehwan Lee, Hyunsung Kim, Minhoo Kang, Seokhyeon Choi, Seung-Goo Kim, Myung-Hoon Choi, Jungju Oh, Yunseong Kim, Haejoon Kim, Sangeun Je, Junhee Ham, Juyeong Yoon, Jaedon Lee, Seonhyeok Park, Youngseob Park, Jaebong Lee, Boeui Hong, Jaehun Ryu, Hyunseok Ko, Kwanghyun Chung, Jongho Choi, Sunwook Jung, Yashael Faith Arthanto, Jonghyeon Kim, Heejin Cho, Hyebin Jeong, Sungmin Choi, Sujin Han, Junkyu Park, Kwangbae Lee, Sung-Il Bae, Jaeho Bang, Kyeong-Jae Lee, Yeongsang Jang, Jungchul Park, Sanggyu Park, Jueon Park, Hyein Shin, Sunghyun Park, Jinwook Oh:
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications. ISSCC 2024: 42-44 - [i1]Kwantae Kim, Changhyeon Kim, Sungpill Choi, Hoi-Jun Yoo:
A 0.5V, 6.2μW, 0.059mm2 Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing. CoRR abs/2402.03533 (2024) - 2020
- [j7]Dongseok Im
, Donghyeon Han
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation. IEEE Trans. Circuits Syst. 67-I(10): 3471-3483 (2020) - [j6]Kyuho Jason Lee
The Development of Silicon for AI: Different Design Approaches. IEEE Trans. Circuits Syst. 67-I(12): 4719-4732 (2020) - [c18]Dongseok Im, Sanghoon Kang, Donghyeon Han, Sungpill Choi, Hoi-Jun Yoo:
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices. VLSI Circuits 2020: 1-2 - [c17]Kwantae Kim
A 0.5V, 6.2μW, 0.059mm2 Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j5]Sungpill Choi
CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(4): 598-611 (2019) - [c16]Sungpill Choi, Kyeongryeol Bong, Donghyeon Han, Hoi-Jun Yoo:
CNNP-v2: An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture. AICAS 2019: 38-41 - [c15]Dongseok Im, Donghyeon Han, Sungpill Choi, Sanghoon Kang, Hoi-Jun Yoo:
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices. ISCAS 2019: 1-5 - [c14]Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sungpill Choi, Youngwoo Kim, Hoi-Jun Yoo:
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression. ISSCC 2019: 136-138 - 2018
- [j4]Kyeongryeol Bong
A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector. IEEE J. Solid State Circuits 53(1): 115-123 (2018) - [c13]Donghyeon Han, Jinsu Lee, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices. ISCAS 2018: 1-5 - [c12]Juhyoung Lee, Changhyeon Kim, Sungpill Choi, Dongjoo Shin, Sanghoon Kang, Hoi-Jun Yoo:
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices. ISCAS 2018: 1-5 - [c11]Sungpill Choi, Jinsu Lee, Kyuho Jason Lee
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. ISSCC 2018: 220-222 - 2017
- [j3]Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Hoi-Jun Yoo:
Low-Power Convolutional Neural Network Processor for a Face-Recognition System. IEEE Micro 37(6): 30-38 (2017) - [c10]Changhyeon Kim, Kyeongryeol Bong, Injoon Hong, Kyuho Jason Lee
An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications. ESSCIRC 2017: 255-258 - [c9]Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Sanghoon Kang, Youchang Kim, Hoi-Jun Yoo:
14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector. ISSCC 2017: 248-249 - 2016
- [j2]Changhyeon Kim, Kyeongryeol Bong, Sungpill Choi, Kyuho Jason Lee
A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2180-2188 (2016) - [c8]Sungpill Choi, Seongwook Park, Hoi-Jun Yoo:
A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface. A-SSCC 2016: 257-260 - [c7]Changhyeon Kim, Kyeongryeol Bong, Sungpill Choi, Hoi-Jun Yoo:
A 43.7 mW 94 fps CMOS image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation. ISCAS 2016: 1418-1421 - [c6]Seongwook Park, Sungpill Choi, Jinmook Lee, Minseo Kim, Junyoung Park, Hoi-Jun Yoo:
14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses. ISSCC 2016: 254-255 - 2015
- [j1]Seongwook Park, Junyoung Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications. IEEE Trans. Biomed. Circuits Syst. 9(6): 838-848 (2015) - [c5]Gyeonghoon Kim, Sungpill Choi, Hoi-Jun Yoo:
K-glass: Real-time markerless augmented reality smart glasses platform. ICIT 2015: 1712-1717 - [c4]Sungpill Choi, Seongwook Park, Gyeonghoon Kim, Hoi-Jun Yoo:
A 124.9fps memory-efficient hand segmentation processor for hand gesture in mobile devices. ISCAS 2015: 742-745 - [c3]Seongwook Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications. ISSCC 2015: 1-3 - 2014
- [c2]Gyeonghoon Kim, Seongwook Park, Kyuho Jason Lee
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler. COOL Chips 2014: 1-3 - [c1]Gyeonghoon Kim, Youchang Kim
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications. ISSCC 2014: 182-183
Coauthor Index
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